mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
39932105f0
This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
7 lines
306 B
ArmAsm
7 lines
306 B
ArmAsm
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbr < %s 2>&1 | FileCheck %s
|
|
|
|
# Too many operands
|
|
crc32.d t0, t1, t2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
|
|
# Too many operands
|
|
crc32c.d t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
|