1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 12:02:58 +02:00
llvm-mirror/test/CodeGen
Matthias Braun 18562ab366 CodeGen: Add DetectDeadLanes pass.
The DetectDeadLanes pass performs a dataflow analysis of used/defined
subregister lanes across COPY instructions and instructions that will
get lowered to copies. It detects dead definitions and uses reading
undefined values which are obscured by COPY and subregister usage.

These dead definitions cause trouble in the register coalescer which
cannot deal with definitions suddenly becoming dead after coalescing
COPY instructions.

For now the pass only adds dead and undef flags to machine operands. It
should be possible to extend it in the future to remove the dead
instructions and redo the analysis for the affected virtual
registers.

Differential Revision: http://reviews.llvm.org/D18427

llvm-svn: 267851
2016-04-28 03:07:16 +00:00
..
AArch64 [AArch64] Set correct successors in CMPXCHG pseudo expansion. 2016-04-27 20:33:02 +00:00
AMDGPU CodeGen: Add DetectDeadLanes pass. 2016-04-28 03:07:16 +00:00
ARM [ARM] Set correct successors in CMPXCHG pseudo expansion. 2016-04-27 20:32:54 +00:00
BPF
CPP
Generic Introduce llvm.load.relative intrinsic. 2016-04-22 21:18:02 +00:00
Hexagon [Tail duplication] Handle source registers with subregisters 2016-04-26 18:36:34 +00:00
Inputs [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
Lanai [lanai] Add subword scheduling itineraries. 2016-04-20 18:28:55 +00:00
Mips [Mips] Add support for llvm.thread.pointer intrinsic. 2016-04-27 17:21:49 +00:00
MIR tests: tweak MIR for ARM tests to correct MI issues 2016-04-26 17:54:21 +00:00
MSP430
NVPTX [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
PowerPC [ppc64] fix bug in prologue that mfocrf's cr operand should be explict state instead of implicit 2016-04-27 02:59:28 +00:00
SPARC [SPARC] [SSP] Add support for LOAD_STACK_GUARD. 2016-04-26 10:37:14 +00:00
SystemZ [SystemZ] Support Swift Calling Convention 2016-04-28 00:17:23 +00:00
Thumb [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
Thumb2
WebAssembly [WebAssembly] Account for implicit operands when computing operand indices. 2016-04-26 01:40:56 +00:00
WinEH [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
X86 [X86] Enable the post-RA-scheduler for clang's default 32-bit cpu. 2016-04-27 22:52:35 +00:00
XCore [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00