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c71feceb04
Author: obucina llvm-svn: 253567
32 lines
1.4 KiB
ArmAsm
32 lines
1.4 KiB
ArmAsm
# RUN: not llvm-mc %s -arch=mips -mcpu=mips32 -show-encoding 2> %t1
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# RUN: FileCheck %s < %t1
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# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 -show-encoding 2> %t1
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# RUN: FileCheck %s < %t1
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# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r3 -show-encoding 2> %t1
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# RUN: FileCheck %s < %t1
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# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r5 -show-encoding 2> %t1
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# RUN: FileCheck %s < %t1
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# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 -show-encoding 2> %t1
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# RUN: FileCheck %s < %t1
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.text
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foo:
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drol $4,$5
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# CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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drol $4,$5,$6
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# CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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drol $4,0
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# CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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drol $4,$5,0
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# CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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dror $4,$5
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# CHECK: [[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
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dror $4,$5,$6
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# CHECK: [[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
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dror $4,0
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# CHECK: [[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
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dror $4,$5,0
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# CHECK: [[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
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