mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 03:53:04 +02:00
bd51d0c9b1
Part 1 was submitted in http://reviews.llvm.org/D15134. Changes in this part: * X86RegisterInfo.td, X86RecognizableInstr.cpp: Add FR128 register class. * X86CallingConv.td: Pass f128 values in XMM registers or on stack. * X86InstrCompiler.td, X86InstrInfo.td, X86InstrSSE.td: Add instruction selection patterns for f128. * X86ISelLowering.cpp: When target has MMX registers, configure MVT::f128 in FR128RegClass, with TypeSoftenFloat action, and custom actions for some opcodes. Add missed cases of MVT::f128 in places that handle f32, f64, or vector types. Add TODO comment to support f128 type in inline assembly code. * SelectionDAGBuilder.cpp: Fix infinite loop when f128 type can have VT == TLI.getTypeToTransformTo(Ctx, VT). * Add unit tests for x86-64 fp128 type. Differential Revision: http://reviews.llvm.org/D11438 llvm-svn: 255558
15 lines
465 B
LLVM
15 lines
465 B
LLVM
; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx | FileCheck %s
|
|
; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx | FileCheck %s
|
|
|
|
; __float128 myFP128 = 1.0L; // x86_64-linux-android
|
|
@myFP128 = global fp128 0xL00000000000000003FFF000000000000, align 16
|
|
|
|
define void @set_FP128(fp128 %x) {
|
|
entry:
|
|
store fp128 %x, fp128* @myFP128, align 16
|
|
ret void
|
|
; CHECK-LABEL: set_FP128:
|
|
; CHECK: movaps %xmm0, myFP128(%rip)
|
|
; CHECK-NEXT: retq
|
|
}
|