Thomas Lively 67397ff9ab [WebAssembly] Renumber SIMD opcodes ... Summary: As described in https://github.com/WebAssembly/simd/pull/209. This is the final reorganization of the SIMD opcode space before standardization. It has been landed in concert with corresponding changes in other projects in the WebAssembly SIMD ecosystem. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D79224		2020-05-01 17:20:49 -07:00
..
AArch64	[AArch64] Remove inexistent system register ERXTS_EL1	2020-04-29 16:43:48 +01:00
AMDGPU	Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""	2020-02-13 10:16:06 -08:00
ARC
ARM	[AArch32] Armv8.6a Matrix Mul Assembly Parsing Support	2020-04-24 15:54:06 +01:00
Hexagon
Lanai
Mips	[mips] Implement Octeon+ saa and saad instructions	2019-11-07 13:58:50 +03:00
MSP430
PowerPC	[llvm] Fix missing FileCheck directive colons	2020-04-06 09:59:08 -06:00
RISCV	[RISCV] Implement evaluateBranch	2020-04-09 15:11:55 +01:00
Sparc
SystemZ
WebAssembly	[WebAssembly] Renumber SIMD opcodes	2020-05-01 17:20:49 -07:00
X86	[X86] Add TSXLDTRK instructions.	2020-04-09 13:17:29 +08:00
XCore