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llvm-mirror/test/Transforms/SLPVectorizer
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Matt Arsenault 3655fd0fd3 AMDGPU: Allow vectorization of round intrinsic 
There seems to be a small benefit to the legalized sequence for v2f16
round with packed instructions, so allow vectorizing it by reducing
the cost.

An unintended side effect is vectorization of f32 round also
happens. The current FMA logic seems off to me, and isn't checking for
packed instructions.
2020-03-23 17:00:41 -04:00
..
AArch64
[SLPVectorizer][SVE] Bail out early for scalable vector.
2020-03-13 11:23:31 -07:00
AMDGPU
AMDGPU: Allow vectorization of round intrinsic
2020-03-23 17:00:41 -04:00
ARM
Revert "Temporarily Revert "Add basic loop fusion pass.""
2019-04-17 04:52:47 +00:00
NVPTX
Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351
2019-12-24 15:57:33 -08:00
PowerPC
Revert "Temporarily Revert "Add basic loop fusion pass.""
2019-04-17 04:52:47 +00:00
SystemZ
[lit] Delete empty lines at the end of lit.local.cfg NFC
2019-06-17 09:51:07 +00:00
X86
[X86] More accurately model the cost of horizontal reductions.
2020-03-22 14:20:15 -07:00
XCore
Revert "Temporarily Revert "Add basic loop fusion pass.""
2019-04-17 04:52:47 +00:00
int_sideeffect.ll
Revert "Temporarily Revert "Add basic loop fusion pass.""
2019-04-17 04:52:47 +00:00