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Valery Pykhtin 1971061641 [AMDGPU] fix readlane/readfirstlane src vgpr operand type.
For VGPR_32 operand disassembler expects a VGPR register encoded as 0..255 (enum8 src operand).
readfirstlane/readline actually has enum9 operand and this change fixes VGPR_32 to VS_32 (enum9 encoding).

Differential Revision: http://reviews.llvm.org/D18696

llvm-svn: 265670
2016-04-07 13:41:51 +00:00
2016-01-26 21:29:08 +00:00
2016-04-06 17:42:16 +00:00
2014-04-07 03:57:04 +00:00
2014-03-02 13:08:46 +00:00
2016-03-28 18:19:32 +00:00
2016-01-26 21:29:08 +00:00
2016-03-30 22:41:06 +00:00
2016-01-04 19:13:29 +00:00

Low Level Virtual Machine (LLVM)
================================

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