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llvm-mirror/test/CodeGen/X86/misched-ilp.ll
Jakob Stoklund Olesen 43b68b7eb9 Enable SandyBridgeModel for all modern Intel P6 descendants.
All Intel CPUs since Yonah look a lot alike, at least at the granularity
of the scheduling models. We can add more accurate models for
processors that aren't Sandy Bridge if required. Haswell will probably
need its own.

The Atom processor and anything based on NetBurst is completely
different. So are the non-Intel chips.

llvm-svn: 178080
2013-03-26 22:19:12 +00:00

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725 B
LLVM

; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=nocona -enable-misched -misched=ilpmax | FileCheck -check-prefix=MAX %s
; RUN: llc < %s -mtriple=x86_64-apple-macosx -mcpu=nocona -enable-misched -misched=ilpmin | FileCheck -check-prefix=MIN %s
;
; Basic verification of the ScheduleDAGILP metric.
;
; MAX: addss
; MAX: addss
; MAX: addss
; MAX: subss
; MAX: addss
;
; MIN: addss
; MIN: addss
; MIN: subss
; MIN: addss
; MIN: addss
define float @ilpsched(float %a, float %b, float %c, float %d, float %e, float %f) nounwind uwtable readnone ssp {
entry:
%add = fadd float %a, %b
%add1 = fadd float %c, %d
%add2 = fadd float %e, %f
%add3 = fsub float %add1, %add2
%add4 = fadd float %add, %add3
ret float %add4
}