llvm-mirror

mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00

History

Adrian Prantl 198732da57 Ignore metainstructions during the shrink wrap analysis Shrink wrapping should ignore DBG_VALUEs referring to frame indices, since the presence of debug information must not affect code generation. Differential Revision: https://reviews.llvm.org/D41187 llvm-svn: 320606		2017-12-13 19:10:54 +00:00
..
AArch64	[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output	2017-11-30 12:12:19 +00:00
AMDGPU	MIR: Print the register class or bank in vreg defs	2017-10-24 18:04:54 +00:00
ARM	[CodeGen] Always use `printReg` to print registers in both MIR and debug	2017-11-30 16:12:24 +00:00
Generic
Hexagon
Mips
NVPTX	MIR: Print the register class or bank in vreg defs	2017-10-24 18:04:54 +00:00
PowerPC
X86	Ignore metainstructions during the shrink wrap analysis	2017-12-13 19:10:54 +00:00
README

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.