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llvm-mirror/test/MC/Mips/macro-divu-bad.s
Simon Dardis ea9109c75f [mips] divide macro instruction cleanup.
Clean up the implementation of divide macro expansion by getting rid of a
FIXME regarding magic numbers and branch instructions. Match GAS' behaviour
for expansion of ddiv / div in the two and three operand cases. Add the two
operand alias for MIPSR6. Finally, optimize macro expansion cases where the
divisior is the $zero register.

Reviewers: slthakur

Differential Revision: https://reviews.llvm.org/D29887

llvm-svn: 294960
2017-02-13 16:06:48 +00:00

19 lines
639 B
ArmAsm

# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
# RUN: FileCheck %s --check-prefix=R6
# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6
# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
# RUN: FileCheck %s --check-prefix=NOT-R6
.text
divu $25, 11
# R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
divu $25, $0
# NOT-R6: :[[@LINE-1]]:3: warning: division by zero
divu $0,$0
# NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero