Alex Bradbury 199da8cd74 [RISCV] Add some missing expansions for floating-point intrinsics ... A number of intrinsics, such as llvm.sin.f32, would result in a failure to select. This patch adds expansions for the relevant selection DAG nodes, as well as exhaustive testing for all f32 and f64 intrinsics. The codegen for FMA remains a TODO item, pending support for the various RISC-V FMA instruction variants. The llvm.minimum.f32.* and llvm.maximum.* tests are commented-out, pending upstream support for target-independent expansion, as discussed in http://lists.llvm.org/pipermail/llvm-dev/2018-November/127408.html. Differential Revision: https://reviews.llvm.org/D54034 Patch by Luís Marques. llvm-svn: 346034		2018-11-02 19:50:38 +00:00
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AsmParser	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
Disassembler	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
InstPrinter	[RISCV] Fix disassembling of fence instruction with invalid field	2018-10-11 22:49:13 +00:00
MCTargetDesc	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
TargetInfo
Utils	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
CMakeLists.txt	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
LLVMBuild.txt	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
RISCV.h	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
RISCV.td	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
RISCVAsmPrinter.cpp	Revert "[RISCV] implement li pseudo instruction"	2018-04-18 19:02:31 +00:00
RISCVCallingConv.td	[RISCV] Add support for _interrupt attribute	2018-07-26 17:49:43 +00:00
RISCVExpandPseudoInsts.cpp	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
RISCVFrameLowering.cpp	[RISCV] Fix std::advance slowness	2018-08-24 23:13:59 +00:00
RISCVFrameLowering.h
RISCVInstrFormats.td	[RISCV] AsmParser support for the li pseudo instruction	2018-06-07 15:35:47 +00:00
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp	[RISCV] Remove overzealous is64Bit checks	2018-10-04 14:30:03 +00:00
RISCVInstrInfo.h	[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot	2018-04-26 15:34:27 +00:00
RISCVInstrInfo.td	[RISCV] Use PatFrags for variable shift patterns	2018-10-25 12:45:20 +00:00
RISCVInstrInfoA.td	[RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo td	2018-10-03 11:14:26 +00:00
RISCVInstrInfoC.td	[RISCV] Compress addiw rd, x0, simm6 to c.li rd, simm6	2018-10-06 06:09:46 +00:00
RISCVInstrInfoD.td	[RISCV] Gate float<->int and double<->int conversion patterns on IsRV32	2018-10-03 11:35:22 +00:00
RISCVInstrInfoF.td	[RISCV] Gate float<->int and double<->int conversion patterns on IsRV32	2018-10-03 11:35:22 +00:00
RISCVInstrInfoM.td
RISCVISelDAGToDAG.cpp	[RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombine	2018-10-03 23:30:16 +00:00
RISCVISelLowering.cpp	[RISCV] Add some missing expansions for floating-point intrinsics	2018-11-02 19:50:38 +00:00
RISCVISelLowering.h	[RISCV][NFC] Fix naming of RISCVISelLowering::{LowerRETURNADDR,LowerFRAMEADDR}	2018-10-04 05:27:50 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv	2018-04-12 05:34:25 +00:00
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp	Test commit.	2018-08-02 05:38:18 +00:00
RISCVRegisterInfo.cpp	[RISCV] Add support for _interrupt attribute	2018-07-26 17:49:43 +00:00
RISCVRegisterInfo.h	[RISCV] Set isReMaterializable on ADDI and LUI instructions	2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.td	[RISCV] Lower the tail pseudoinstruction	2018-05-23 22:44:08 +00:00
RISCVSubtarget.cpp
RISCVSubtarget.h	[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation	2018-05-15 01:28:50 +00:00
RISCVSystemOperands.td	[RISCV] Support named operands for CSR instructions.	2018-10-04 21:50:54 +00:00
RISCVTargetMachine.cpp	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h