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llvm-mirror/lib/CodeGen/SelectionDAG
Roman Lebedev 19d08eac86 [TLI] prepareSREMEqFold(): use correct VT for the final VSELECT (PR51133)
We were using the wrong VT for this final VSELECT,
it should be in the final comparison VT,
not the source value's VT.

Fixes https://bugs.llvm.org/show_bug.cgi?id=51133
2021-07-19 16:44:00 +03:00
..
CMakeLists.txt
DAGCombiner.cpp [DAG] DAGCombiner::foldSelectOfBinops - propagate the common flags to the merged binop 2021-07-18 18:38:59 +01:00
FastISel.cpp [InstrRef][FastISel] Support emitting DBG_INSTR_REF from fast-isel 2021-07-16 13:56:15 +01:00
FunctionLoweringInfo.cpp
InstrEmitter.cpp [DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations 2021-07-06 18:31:38 +01:00
InstrEmitter.h [DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations 2021-07-06 18:31:38 +01:00
LegalizeDAG.cpp [TargetLowering][AArch64][SVE] Take into account accessed type when clamping address 2021-06-30 13:30:18 +01:00
LegalizeFloatTypes.cpp Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
LegalizeIntegerTypes.cpp [SelectionDAG][RISCV] Support @llvm.vscale.i64() on 32-bit targets. 2021-07-12 14:53:42 -07:00
LegalizeTypes.cpp
LegalizeTypes.h [SelectionDAG][RISCV] Support @llvm.vscale.i64() on 32-bit targets. 2021-07-12 14:53:42 -07:00
LegalizeTypesGeneric.cpp
LegalizeVectorOps.cpp [AArch64][SVE] Add support for fixed length MSCATTER/MGATHER 2021-07-01 12:13:59 +01:00
LegalizeVectorTypes.cpp Revert "[llvm] Add enum iteration to Sequence" 2021-07-13 16:44:42 +00:00
ResourcePriorityQueue.cpp
ScheduleDAGFast.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp
ScheduleDAGSDNodes.h
ScheduleDAGVLIW.cpp
SDNodeDbgValue.h
SelectionDAG.cpp [X86] Remove incorrect use of known bits in shuffle simplification. 2021-07-18 18:13:11 -07:00
SelectionDAGAddressAnalysis.cpp
SelectionDAGBuilder.cpp [SelectionDAG] Add an overload of getStepVector that assumes step 1. 2021-07-14 11:37:01 -07:00
SelectionDAGBuilder.h SwiftTailCC: teach verifier musttail rules applicable to this CC. 2021-05-28 11:12:00 +01:00
SelectionDAGDumper.cpp [ISel] Port AArch64 SABD and UABD to DAGCombine 2021-06-26 19:34:16 +01:00
SelectionDAGISel.cpp [DebugInfo][InstrRef][3/4] Produce DBG_INSTR_REFs for all variable locations 2021-07-06 18:31:38 +01:00
SelectionDAGPrinter.cpp
SelectionDAGTargetInfo.cpp
StatepointLowering.cpp [Statepoint Lowering] Cleanup: remove unused option statepoint-always-spill-base. 2021-05-18 12:15:15 +07:00
StatepointLowering.h
TargetLowering.cpp [TLI] prepareSREMEqFold(): use correct VT for the final VSELECT (PR51133) 2021-07-19 16:44:00 +03:00