..
AsmParser
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
Disassembler
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
MCTargetDesc
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
TargetInfo
Utils
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
AMDGPU.h
AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
2020-05-31 20:40:14 -04:00
AMDGPU.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
AMDGPUAliasAnalysis.cpp
AMDGPUAliasAnalysis.h
Remove orphan AMDGPUAAResult::Aliases and AMDGPUAAResult::PathAliases declarations. NFC.
2020-06-25 16:00:44 +01:00
AMDGPUAlwaysInlinePass.cpp
AMDGPUAnnotateKernelFeatures.cpp
AMDGPU: Annotate functions that have stack objects
2020-05-19 18:51:00 -04:00
AMDGPUAnnotateUniformValues.cpp
AMDGPU: Fix not using scalar loads for global reads in shaders
2020-06-02 09:49:23 -04:00
AMDGPUArgumentUsageInfo.cpp
AMDGPUArgumentUsageInfo.h
AMDGPUAsmPrinter.cpp
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
AMDGPUAsmPrinter.h
AMDGPUAtomicOptimizer.cpp
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
2020-05-29 17:54:17 -07:00
AMDGPUCallingConv.td
AMDGPUCallLowering.cpp
[Alignment][NFC] Transition and simplify calls to DL::getABITypeAlignment
2020-07-01 14:31:56 +00:00
AMDGPUCallLowering.h
AMDGPUCodeGenPrepare.cpp
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
AMDGPUCombine.td
AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
2020-05-31 20:40:14 -04:00
AMDGPUExportClustering.cpp
AMDGPUExportClustering.h
AMDGPUFeatures.td
AMDGPU: Change internal tracking of wave size
2020-06-01 17:55:08 -04:00
AMDGPUFixFunctionBitcasts.cpp
AMDGPU.h - reduce TargetMachine.h include. NFC.
2020-05-24 15:27:41 +01:00
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUGenRegisterBankInfo.def
AMDGPUGISel.td
AMDGPUGlobalISelUtils.cpp
AMDGPUGlobalISelUtils.h
AMDGPUHSAMetadataStreamer.cpp
[Alignment][NFC] Transition and simplify calls to DL::getABITypeAlignment
2020-07-01 14:31:56 +00:00
AMDGPUHSAMetadataStreamer.h
[Alignment][NFC] Transition and simplify calls to DL::getABITypeAlignment
2020-07-01 14:31:56 +00:00
AMDGPUInline.cpp
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td
AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
2020-06-16 21:06:25 -04:00
AMDGPUInstructions.td
AMDGPU: Add llvm.amdgcn.sqrt intrinsic
2020-06-26 15:07:07 -04:00
AMDGPUInstructionSelector.cpp
AMDGPU/GlobalISel: Select icmp intrinsic
2020-06-30 10:57:41 +02:00
AMDGPUInstructionSelector.h
AMDGPU/GlobalISel: Select icmp intrinsic
2020-06-30 10:57:41 +02:00
AMDGPUISelDAGToDAG.cpp
[SDAG] Add new AssertAlign ISD node.
2020-06-23 00:51:11 -04:00
AMDGPUISelLowering.cpp
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
AMDGPUISelLowering.h
AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
2020-06-16 21:06:25 -04:00
AMDGPULegalizerInfo.cpp
AMDGPU/GlobalISel: Fix some legalization of < dword vector stores
2020-06-26 18:07:39 -04:00
AMDGPULegalizerInfo.h
AMDGPU/GlobalISel: Legalize 64-bit G_SDIV/G_SREM
2020-06-24 11:39:45 -04:00
AMDGPULibCalls.cpp
[AMDGPU][NFC] Skip processing intrinsics that do not become real instructions
2020-06-09 03:45:33 +03:00
AMDGPULibFunc.cpp
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
2020-05-29 17:54:17 -07:00
AMDGPULibFunc.h
AMDGPULibFunc - fix include order. NFC.
2020-05-24 13:25:59 +01:00
AMDGPULowerIntrinsics.cpp
AMDGPULowerKernelArguments.cpp
[Alignment][NFC] Transition and simplify calls to DL::getABITypeAlignment
2020-07-01 14:31:56 +00:00
AMDGPULowerKernelAttributes.cpp
AMDGPUMachineCFGStructurizer.cpp
AMDGPUMachineFunction.cpp
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
AMDGPUMachineFunction.h
Remove GlobalValue::getAlignment().
2020-06-23 19:13:42 -07:00
AMDGPUMachineModuleInfo.cpp
AMDGPUMachineModuleInfo.h
AMDGPUMacroFusion.cpp
AMDGPUMacroFusion.h
AMDGPUMCInstLower.cpp
AMDGPUOpenCLEnqueuedBlockLowering.cpp
AMDGPUPerfHintAnalysis.cpp
AMDGPU.h - reduce TargetMachine.h include. NFC.
2020-05-24 15:27:41 +01:00
AMDGPUPerfHintAnalysis.h
AMDGPUPostLegalizerCombiner.cpp
AMDGPU/GlobalISel: Fix asserts on non-s32 sitofp/uitofp sources
2020-06-23 10:00:35 -04:00
AMDGPUPreLegalizerCombiner.cpp
[gicombiner] Allow generated combiners to store additional members
2020-06-16 14:47:04 -07:00
AMDGPUPrintfRuntimeBinding.cpp
[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
2020-05-29 17:54:17 -07:00
AMDGPUPromoteAlloca.cpp
[AMDGPU] Limit promote alloca to vector with VGPR budget
2020-07-01 15:57:24 -07:00
AMDGPUPropagateAttributes.cpp
AMDGPUPTNote.h
AMDGPURegBankCombiner.cpp
[gicombiner] Allow generated combiners to store additional members
2020-06-16 14:47:04 -07:00
AMDGPURegisterBankInfo.cpp
AMDGPU/GlobalISel: Select init_exec intrinsic
2020-07-01 11:50:59 +02:00
AMDGPURegisterBankInfo.h
AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads
2020-06-15 11:33:16 -04:00
AMDGPURegisterBanks.td
AMDGPURewriteOutArguments.cpp
AMDGPUSearchableTables.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
AMDGPUSubtarget.cpp
[AMDGPU] Control num waves per EU for implicit work-group size
2020-07-01 22:53:52 -04:00
AMDGPUSubtarget.h
AMDGPU: Don't pass MachineFunction if only the IR Function is used
2020-06-18 11:06:46 -04:00
AMDGPUTargetMachine.cpp
[AMDGPU] Simplify GCNPassConfig::addOptimizedRegAlloc. NFC.
2020-06-17 15:56:15 +01:00
AMDGPUTargetMachine.h
AMDGPU: Fix wrong null value for private address space
2020-05-26 16:35:13 -04:00
AMDGPUTargetObjectFile.cpp
AMDGPUTargetObjectFile.h
AMDGPUTargetObjectFile.h - remove unnecessary includes. NFC.
2020-05-24 13:57:02 +01:00
AMDGPUTargetTransformInfo.cpp
[Alignment][NFC] Migrate TTI::isLegalToVectorize{Load,Store}Chain to Align
2020-06-26 14:14:27 +00:00
AMDGPUTargetTransformInfo.h
[Alignment][NFC] Migrate TTI::isLegalToVectorize{Load,Store}Chain to Align
2020-06-26 14:14:27 +00:00
AMDGPUUnifyDivergentExitNodes.cpp
Correctly report modified status for AMDGPUUnifyDivergentExitNodes
2020-06-05 19:49:37 +01:00
AMDGPUUnifyMetadata.cpp
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h
BUFInstructions.td
AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
2020-06-18 14:12:19 -04:00
CaymanInstructions.td
CMakeLists.txt
AMDGPU/GlobalISel: Add stub reg-bank aware combiner pass
2020-05-31 20:40:14 -04:00
DSInstructions.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
EvergreenInstructions.td
FLATInstructions.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
GCNDPPCombine.cpp
AMDGPU: Use IsSSA property check instead of asserting on isSSA
2020-06-29 10:05:23 -04:00
GCNHazardRecognizer.cpp
GCNHazardRecognizer.h
GCNILPSched.cpp
GCNIterativeScheduler.cpp
GCNIterativeScheduler.h
GCNMinRegStrategy.cpp
SmallPtrSet::find -> SmallPtrSet::count
2020-06-07 22:38:08 +02:00
GCNNSAReassign.cpp
GCNProcessors.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
GCNRegBankReassign.cpp
[AMDGPU] Use std::pair to return two values. NFC.
2020-06-26 11:47:12 +01:00
GCNRegPressure.cpp
GCNRegPressure.h
GCNSchedStrategy.cpp
GCNSchedStrategy.h
LLVMBuild.txt
MIMGInstructions.td
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
R600.td
R600AsmPrinter.cpp
R600AsmPrinter.h
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600FrameLowering.cpp
R600FrameLowering.h
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td
R600ISelLowering.cpp
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OpenCLImageTypeLoweringPass.cpp
R600OptimizeVectorRegisters.cpp
AMDGPU: Use Register
2020-06-30 12:13:08 -04:00
R600Packetizer.cpp
R600Processors.td
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R700Instructions.td
SIAddIMGInit.cpp
SIAnnotateControlFlow.cpp
SIDefines.h
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
SIFixSGPRCopies.cpp
[AMDGPU] Reject moving PHI to VALU if the only VGPR input originated from move immediate
2020-05-28 19:25:51 +03:00
SIFixupVectorISel.cpp
SIFixVGPRCopies.cpp
SIFoldOperands.cpp
AMDGPU: Clear subreg when folding immediate copies
2020-07-01 13:59:13 -04:00
SIFormMemoryClauses.cpp
SIFrameLowering.cpp
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
SIFrameLowering.h
SIInsertHardClauses.cpp
[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes
2020-06-01 22:52:34 +05:30
SIInsertSkips.cpp
[AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips.
2020-06-29 20:41:53 +05:30
SIInsertWaitcnts.cpp
[AMDGPU] Skip CFIInstructions in SIInsertWaitcnts
2020-06-17 12:41:03 -04:00
SIInstrFormats.td
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
SIInstrInfo.cpp
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
SIInstrInfo.h
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
SIInstrInfo.td
Revert "[AMDGPU] Enable compare operations to be selected by divergence"
2020-06-24 11:21:30 -04:00
SIInstructions.td
AMDGPU/GlobalISel: Select init_exec intrinsic
2020-07-01 11:50:59 +02:00
SIISelLowering.cpp
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
SIISelLowering.h
[Alignment][NFC] Migrate AMDGPU backend to Align
2020-06-29 11:56:06 +00:00
SILoadStoreOptimizer.cpp
AMDGPU: Use IsSSA property check instead of asserting on isSSA
2020-06-29 10:05:23 -04:00
SILowerControlFlow.cpp
SILowerI1Copies.cpp
SILowerSGPRSpills.cpp
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
SIMachineFunctionInfo.cpp
[AMDGPU] Spill more than wavesize CSR SGPRs
2020-07-01 07:40:47 +00:00
SIMachineFunctionInfo.h
SIMachineScheduler.cpp
SIMachineScheduler.h
SIMemoryLegalizer.cpp
SIModeRegister.cpp
[AMDGPU] Avoid redundant mode register writes
2020-06-24 14:11:29 +01:00
SIOptimizeExecMasking.cpp
SIOptimizeExecMaskingPreRA.cpp
SIPeepholeSDWA.cpp
AMDGPU: Fix dropping MI flags when rewriting instructions
2020-05-27 13:27:06 -04:00
SIPostRABundler.cpp
AMDGPU: Do not bundle inline asm
2020-06-14 13:24:50 -04:00
SIPreAllocateWWMRegs.cpp
SIPreEmitPeephole.cpp
[AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips.
2020-06-29 20:41:53 +05:30
SIProgramInfo.h
SIRegisterInfo.cpp
AMDGPU: Use Register
2020-06-30 12:13:08 -04:00
SIRegisterInfo.h
[NFC] Move getAll{S,V}GPR{32,128} methods to SIFrameLowering
2020-06-17 12:08:09 -04:00
SIRegisterInfo.td
AMDGPU: Define mode register
2020-05-23 13:24:42 -04:00
SIRemoveShortExecBranches.cpp
SISchedule.td
[AMDGPU] More accurate gfx10 latencies
2020-06-04 10:29:32 +01:00
SIShrinkInstructions.cpp
[AMDGPU] Add gfx1030 target
2020-06-15 16:18:05 -07:00
SIWholeQuadMode.cpp
[AMDGPU] Update more live intervals in SIWholeQuadMode
2020-06-22 13:50:15 +01:00
SMInstructions.td
AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
2020-06-18 14:12:19 -04:00
SOPInstructions.td
[AMDGPU] Select s_cselect
2020-06-25 10:38:23 +02:00
VIInstrFormats.td
VOP1Instructions.td
AMDGPU: Add llvm.amdgcn.sqrt intrinsic
2020-06-26 15:07:07 -04:00
VOP2Instructions.td
AMDGPU: Don't use 16-bit FP inline constants in integer operands
2020-06-17 19:14:10 -04:00
VOP3Instructions.td
AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
2020-06-16 21:06:25 -04:00
VOP3PInstructions.td
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
VOPCInstructions.td
AMDGPU: Start adding MODE register uses to instructions
2020-05-27 14:47:00 -04:00
VOPInstructions.td
AMDGPU: Set mayRaiseFPException
2020-06-04 17:35:27 -04:00
