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222 lines
7.6 KiB
TableGen
222 lines
7.6 KiB
TableGen
//===-- SISchedule.td - SI Scheduling definitions -------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// MachineModel definitions for Southern Islands (SI)
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//
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//===----------------------------------------------------------------------===//
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def : PredicateProlog<[{
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
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(void)TII;
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}]>;
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def WriteBranch : SchedWrite;
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def WriteExport : SchedWrite;
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def WriteLDS : SchedWrite;
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def WriteSALU : SchedWrite;
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def WriteSMEM : SchedWrite;
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def WriteVMEM : SchedWrite;
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def WriteBarrier : SchedWrite;
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def MIVGPRRead : SchedRead;
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def MIMFMARead : SchedRead;
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// Normal 16 or 32 bit VALU instructions
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def Write32Bit : SchedWrite;
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// Conversion to or from F32 (but not converting F64 to or from F32)
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def WriteFloatCvt : SchedWrite;
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// F16 or F32 transcendental instructions (these are quarter rate)
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def WriteTrans32 : SchedWrite;
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// Other quarter rate VALU instructions
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def WriteQuarterRate32 : SchedWrite;
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def WriteFloatFMA : SchedWrite;
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// Slow quarter rate f64 instruction.
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def WriteDouble : SchedWrite;
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// half rate f64 instruction (same as v_add_f64)
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def WriteDoubleAdd : SchedWrite;
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// Conversion to or from f64 instruction
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def WriteDoubleCvt : SchedWrite;
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// F64 "transcendental" (actually only reciprocal and/or square root)
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// instructions
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def WriteTrans64 : SchedWrite;
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// Half rate 64-bit instructions.
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def Write64Bit : SchedWrite;
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// mAI multipass instructions.
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def Write2PassMAI : SchedWrite;
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def Write8PassMAI : SchedWrite;
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def Write16PassMAI : SchedWrite;
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// FIXME: Should there be a class for instructions which are VALU
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// instructions and have VALU rates, but write to the SALU (i.e. VOPC
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// instructions)
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class SISchedMachineModel : SchedMachineModel {
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let CompleteModel = 1;
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// MicroOpBufferSize = 1 means that instructions will always be added
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// the ready queue when they become available. This exposes them
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// to the register pressure analysis.
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let MicroOpBufferSize = 1;
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let IssueWidth = 1;
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let PostRAScheduler = 1;
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// FIXME:Approximate 2 * branch cost. Try to hack around bad
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// early-ifcvt heuristics. These need improvement to avoid the OOE
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// heuristics.
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int MispredictPenalty = 20;
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}
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def SIFullSpeedModel : SISchedMachineModel;
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def SIQuarterSpeedModel : SISchedMachineModel;
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def GFX10SpeedModel : SISchedMachineModel;
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// XXX: Are the resource counts correct?
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def HWBranch : ProcResource<1> {
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let BufferSize = 1;
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}
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def HWExport : ProcResource<1> {
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let BufferSize = 7; // Taken from S_WAITCNT
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}
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def HWLGKM : ProcResource<1> {
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let BufferSize = 31; // Taken from S_WAITCNT
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}
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def HWSALU : ProcResource<1> {
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let BufferSize = 1;
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}
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def HWVMEM : ProcResource<1> {
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let BufferSize = 15; // Taken from S_WAITCNT
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}
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def HWVALU : ProcResource<1> {
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let BufferSize = 1;
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}
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def HWRC : ProcResource<1> { // Register destination cache
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let BufferSize = 1;
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}
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class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
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int latency> : WriteRes<write, resources> {
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let Latency = latency;
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}
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class HWVALUWriteRes<SchedWrite write, int latency> :
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HWWriteRes<write, [HWVALU], latency>;
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def PredMIReadVGPR : SchedPredicate<[{TII->hasVGPRUses(*MI)}]>;
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def MIReadVGPR : SchedReadVariant<[
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SchedVar<PredMIReadVGPR, [MIVGPRRead]>,
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SchedVar<NoSchedPred, [ReadDefault]>]>;
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// The latency numbers are taken from AMD Accelerated Parallel Processing
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// guide. They may not be accurate.
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// The latency values are 1 / (operations / cycle) / 4.
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multiclass SICommonWriteRes {
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def : HWWriteRes<WriteBranch, [HWBranch], 8>;
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def : HWWriteRes<WriteExport, [HWExport], 4>;
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def : HWWriteRes<WriteLDS, [HWLGKM], 5>; // Can be between 2 and 64
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def : HWWriteRes<WriteSALU, [HWSALU], 1>;
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def : HWWriteRes<WriteSMEM, [HWLGKM], 5>;
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def : HWWriteRes<WriteVMEM, [HWVMEM], 80>;
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def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???
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def : HWVALUWriteRes<Write32Bit, 1>;
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def : HWVALUWriteRes<Write64Bit, 2>;
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def : HWVALUWriteRes<WriteFloatCvt, 4>;
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def : HWVALUWriteRes<WriteTrans32, 4>;
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def : HWVALUWriteRes<WriteQuarterRate32, 4>;
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def : HWVALUWriteRes<Write2PassMAI, 2>;
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def : HWVALUWriteRes<Write8PassMAI, 8>;
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def : HWVALUWriteRes<Write16PassMAI, 16>;
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def : ReadAdvance<MIVGPRRead, -2>;
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def : InstRW<[Write64Bit, MIReadVGPR], (instregex "^V_ACCVGPR_WRITE_B32$")>;
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// Technically mfma reads can be from 0 to 4 cycles but that does not make
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// sense to model because its register setup is huge. In particular if we
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// properly model read advance as -2 for a vgpr read it will result in a
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// bad scheduling of acc writes before that mfma. To avoid it we would
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// need to consume 2 or 4 more vgprs to be initialized before the acc
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// write sequence. Just assume worst case here.
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def : ReadAdvance<MIMFMARead, -4>;
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def : InstRW<[Write2PassMAI, MIMFMARead], (instregex "^V_MFMA_..._4X4X")>;
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def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_..._16X16X")>;
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def : InstRW<[Write16PassMAI, MIMFMARead], (instregex "^V_MFMA_..._32X32X")>;
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}
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def PredIsVGPR32Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32}]>;
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def PredIsVGPR64Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32}]>;
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def WriteCopy : SchedWriteVariant<[
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SchedVar<PredIsVGPR32Copy, [Write32Bit]>,
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SchedVar<PredIsVGPR64Copy, [Write64Bit]>,
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SchedVar<NoSchedPred, [WriteSALU]>]>;
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let SchedModel = SIFullSpeedModel in {
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defm : SICommonWriteRes;
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def : HWVALUWriteRes<WriteFloatFMA, 1>;
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def : HWVALUWriteRes<WriteDouble, 4>;
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def : HWVALUWriteRes<WriteDoubleAdd, 2>;
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def : HWVALUWriteRes<WriteDoubleCvt, 4>;
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def : HWVALUWriteRes<WriteTrans64, 4>;
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def : InstRW<[WriteCopy], (instrs COPY)>;
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} // End SchedModel = SIFullSpeedModel
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let SchedModel = SIQuarterSpeedModel in {
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defm : SICommonWriteRes;
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def : HWVALUWriteRes<WriteFloatFMA, 16>;
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def : HWVALUWriteRes<WriteDouble, 16>;
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def : HWVALUWriteRes<WriteDoubleAdd, 8>;
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def : HWVALUWriteRes<WriteDoubleCvt, 4>;
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def : HWVALUWriteRes<WriteTrans64, 16>;
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def : InstRW<[WriteCopy], (instrs COPY)>;
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} // End SchedModel = SIQuarterSpeedModel
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let SchedModel = GFX10SpeedModel in {
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// The latency values are 1 / (operations / cycle).
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// Add 1 stall cycle for VGPR read.
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def : HWWriteRes<Write32Bit, [HWVALU, HWRC], 5>;
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def : HWWriteRes<WriteFloatCvt, [HWVALU, HWRC], 5>;
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def : HWWriteRes<Write64Bit, [HWVALU, HWRC], 6>;
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def : HWWriteRes<WriteTrans32, [HWVALU, HWRC], 10>;
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def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC], 8>;
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def : HWWriteRes<WriteFloatFMA, [HWVALU, HWRC], 5>;
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def : HWWriteRes<WriteDouble, [HWVALU, HWRC], 22>;
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def : HWWriteRes<WriteDoubleAdd, [HWVALU, HWRC], 22>;
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def : HWWriteRes<WriteDoubleCvt, [HWVALU, HWRC], 22>;
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def : HWWriteRes<WriteTrans64, [HWVALU, HWRC], 24>;
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def : HWWriteRes<WriteBranch, [HWBranch], 32>;
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def : HWWriteRes<WriteExport, [HWExport, HWRC], 16>;
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def : HWWriteRes<WriteLDS, [HWLGKM, HWRC], 20>;
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def : HWWriteRes<WriteSALU, [HWSALU, HWRC], 2>;
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def : HWWriteRes<WriteSMEM, [HWLGKM, HWRC], 20>;
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def : HWWriteRes<WriteVMEM, [HWVMEM, HWRC], 320>;
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def : HWWriteRes<WriteBarrier, [HWBranch], 2000>;
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def : InstRW<[WriteCopy], (instrs COPY)>;
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} // End SchedModel = GFX10SpeedModel
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