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207 lines
5.7 KiB
LLVM
207 lines
5.7 KiB
LLVM
; RUN: llc < %s -march=ptx32 | FileCheck %s
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define ptx_device i32 @test_setp_eq_u32_rr(i32 %x, i32 %y) {
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; CHECK: setp.eq.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp eq i32 %x, %y
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_ne_u32_rr(i32 %x, i32 %y) {
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; CHECK: setp.ne.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp ne i32 %x, %y
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_lt_u32_rr(i32 %x, i32 %y) {
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; CHECK: setp.lt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp ult i32 %x, %y
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_le_u32_rr(i32 %x, i32 %y) {
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; CHECK: setp.le.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp ule i32 %x, %y
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_gt_u32_rr(i32 %x, i32 %y) {
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; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp ugt i32 %x, %y
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_ge_u32_rr(i32 %x, i32 %y) {
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; CHECK: setp.ge.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp uge i32 %x, %y
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_lt_s32_rr(i32 %x, i32 %y) {
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; CHECK: setp.lt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp slt i32 %x, %y
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_le_s32_rr(i32 %x, i32 %y) {
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; CHECK: setp.le.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp sle i32 %x, %y
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_gt_s32_rr(i32 %x, i32 %y) {
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; CHECK: setp.gt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp sgt i32 %x, %y
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_ge_s32_rr(i32 %x, i32 %y) {
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; CHECK: setp.ge.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp sge i32 %x, %y
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_eq_u32_ri(i32 %x) {
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; CHECK: setp.eq.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp eq i32 %x, 1
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_ne_u32_ri(i32 %x) {
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; CHECK: setp.ne.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp ne i32 %x, 1
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_lt_u32_ri(i32 %x) {
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; CHECK: setp.eq.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp ult i32 %x, 1
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_le_u32_ri(i32 %x) {
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; CHECK: setp.lt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 2;
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp ule i32 %x, 1
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_gt_u32_ri(i32 %x) {
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; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp ugt i32 %x, 1
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_ge_u32_ri(i32 %x) {
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; CHECK: setp.ne.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp uge i32 %x, 1
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_lt_s32_ri(i32 %x) {
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; CHECK: setp.lt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp slt i32 %x, 1
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_le_s32_ri(i32 %x) {
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; CHECK: setp.lt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 2;
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp sle i32 %x, 1
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_gt_s32_ri(i32 %x) {
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; CHECK: setp.gt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp sgt i32 %x, 1
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_ge_s32_ri(i32 %x) {
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; CHECK: setp.gt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%p = icmp sge i32 %x, 1
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%z = zext i1 %p to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_4_op_format_1(i32 %x, i32 %y, i32 %u, i32 %v) {
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; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
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; CHECK-NEXT: setp.eq.and.u32 p[[P0]], r{{[0-9]+}}, r{{[0-9]+}}, p[[P0]];
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%c = icmp eq i32 %x, %y
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%d = icmp ugt i32 %u, %v
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%e = and i1 %c, %d
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%z = zext i1 %e to i32
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ret i32 %z
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}
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define ptx_device i32 @test_setp_4_op_format_2(i32 %x, i32 %y, i32 %w) {
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; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
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; CHECK-NEXT: setp.eq.and.u32 p[[P0]], r{{[0-9]+}}, r{{[0-9]+}}, !p[[P0]];
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; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
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; CHECK-NEXT: ret;
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%c = trunc i32 %w to i1
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%d = icmp eq i32 %x, %y
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%e = xor i1 %c, 1
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%f = and i1 %d, %e
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%z = zext i1 %f to i32
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ret i32 %z
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}
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