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llvm-mirror/test/MC/Disassembler
Artem Tamazov 1adac220b3 [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.
Added support for sendmsg(MSG[, OP[, STREAM_ID]]) syntax
in s_sendmsg and s_sendmsghalt instructions.
The syntax matches the SP3 assembler/disassembler rules.
That is why implicit inputs (like M0 and EXEC) are not printed
to disassembly output anymore.

sendmsg(...) allows only known message types and attributes,
even if literals are used instead of symbolic names.
However, raw literal (without "sendmsg") still can be used,
and that allows for any 16-bit value.

Tests updated/added.

Differential Revision: http://reviews.llvm.org/D19596

llvm-svn: 268762
2016-05-06 17:48:48 +00:00
..
AArch64 [AArch64] Add ARMv8.2-A FP16 vector instructions 2015-12-08 12:16:10 +00:00
AMDGPU [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax. 2016-05-06 17:48:48 +00:00
ARM [LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC. 2016-04-19 23:51:52 +00:00
Hexagon [Hexagon] Fixing store instructions and reenabling a few more tests. 2015-11-10 00:22:00 +00:00
Lanai [lanai] Add Lanai backend. 2016-03-28 13:09:54 +00:00
Mips [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructions 2016-05-06 08:24:14 +00:00
PowerPC This reverts commit r265505. 2016-04-28 20:00:42 +00:00
Sparc This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
SystemZ [SystemZ] Add SVC instruction 2016-04-11 14:35:39 +00:00
X86 AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling. 2016-02-25 13:30:17 +00:00
XCore Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00