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llvm-mirror/test/MC/AVR/inst-sts.s
Ayke van Laethem a147209ed5 [AVR] Implement disassembly of 32-bit instructions
This needed two fixes:

  * 32-bit instructions were read in the wrong order. The machine code
    swaps the two 16-bit instruction words, which wasn't undone when
    decoding instructions.
  * Jump and call instructions don't encode the lowest address bit,
    which is always zero. Therefore, the address needed to be shifted by
    one to fix that.

Differential Revision: https://reviews.llvm.org/D81961
2020-06-18 11:26:58 +02:00

21 lines
683 B
ArmAsm

; RUN: llvm-mc -triple avr -mattr=sram -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=sram < %s | llvm-objdump -dr --mattr=sram - | FileCheck -check-prefix=CHECK-INST %s
foo:
sts 3, r5
sts 255, r7
sts SYMBOL+1, r25
; CHECK: sts 3, r5 ; encoding: [0x50,0x92,0x03,0x00]
; CHECK: sts 255, r7 ; encoding: [0x70,0x92,0xff,0x00]
; CHECK: sts SYMBOL+1, r25 ; encoding: [0x90,0x93,A,A]
; CHECK: ; fixup A - offset: 2, value: SYMBOL+1, kind: fixup_16
; CHECK-INST: sts 3, r5
; CHECK-INST: sts 255, r7
; CHECK-INST: sts 0, r25
; CHECK-INST: R_AVR_16 SYMBOL+0x1