mirror of
https://github.com/RPCS3/llvm-mirror.git
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4cc3c35fb0
This is similar to the computeKnownBits improvement in rL268479. There's probably more we can do for vector logic instructions, but this should let us see non-splat constant masking ops that can become vector selects instead of and/andn/or sequences. Differential Revision: http://reviews.llvm.org/D21610 llvm-svn: 273459
432 lines
9.0 KiB
LLVM
432 lines
9.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instsimplify -S | FileCheck %s
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define i32 @foo(i32 %x) {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: [[O:%.*]] = and i32 %x, 1
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; CHECK-NEXT: [[N:%.*]] = add i32 [[O]], -1
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; CHECK-NEXT: ret i32 [[N]]
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;
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%o = and i32 %x, 1
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%n = add i32 %o, -1
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%t = ashr i32 %n, 17
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ret i32 %t
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}
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define i1 @exact_lshr_eq_both_zero(i8 %a) {
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; CHECK-LABEL: @exact_lshr_eq_both_zero(
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; CHECK-NEXT: ret i1 true
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;
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%shr = lshr exact i8 0, %a
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%cmp = icmp eq i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @exact_ashr_eq_both_zero(i8 %a) {
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; CHECK-LABEL: @exact_ashr_eq_both_zero(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr exact i8 0, %a
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%cmp = icmp eq i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @nonexact_ashr_eq_both_zero(i8 %a) {
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; CHECK-LABEL: @nonexact_ashr_eq_both_zero(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr i8 0, %a
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%cmp = icmp eq i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @exact_lshr_ne_both_zero(i8 %a) {
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; CHECK-LABEL: @exact_lshr_ne_both_zero(
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; CHECK-NEXT: ret i1 false
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;
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%shr = lshr exact i8 0, %a
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%cmp = icmp ne i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @exact_ashr_ne_both_zero(i8 %a) {
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; CHECK-LABEL: @exact_ashr_ne_both_zero(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr exact i8 0, %a
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%cmp = icmp ne i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @nonexact_lshr_ne_both_zero(i8 %a) {
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; CHECK-LABEL: @nonexact_lshr_ne_both_zero(
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; CHECK-NEXT: ret i1 false
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;
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%shr = lshr i8 0, %a
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%cmp = icmp ne i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @nonexact_ashr_ne_both_zero(i8 %a) {
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; CHECK-LABEL: @nonexact_ashr_ne_both_zero(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr i8 0, %a
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%cmp = icmp ne i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @exact_lshr_eq_last_zero(i8 %a) {
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; CHECK-LABEL: @exact_lshr_eq_last_zero(
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; CHECK-NEXT: ret i1 false
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;
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%shr = lshr exact i8 128, %a
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%cmp = icmp eq i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @exact_ashr_eq_last_zero(i8 %a) {
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; CHECK-LABEL: @exact_ashr_eq_last_zero(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr exact i8 -128, %a
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%cmp = icmp eq i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @nonexact_lshr_eq_both_zero(i8 %a) {
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; CHECK-LABEL: @nonexact_lshr_eq_both_zero(
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; CHECK-NEXT: ret i1 true
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;
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%shr = lshr i8 0, %a
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%cmp = icmp eq i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @exact_lshr_ne_last_zero(i8 %a) {
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; CHECK-LABEL: @exact_lshr_ne_last_zero(
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; CHECK-NEXT: ret i1 true
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;
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%shr = lshr exact i8 128, %a
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%cmp = icmp ne i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @exact_ashr_ne_last_zero(i8 %a) {
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; CHECK-LABEL: @exact_ashr_ne_last_zero(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr exact i8 -128, %a
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%cmp = icmp ne i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @nonexact_lshr_eq_last_zero(i8 %a) {
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; CHECK-LABEL: @nonexact_lshr_eq_last_zero(
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; CHECK-NEXT: ret i1 false
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;
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%shr = lshr i8 128, %a
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%cmp = icmp eq i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @nonexact_ashr_eq_last_zero(i8 %a) {
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; CHECK-LABEL: @nonexact_ashr_eq_last_zero(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr i8 -128, %a
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%cmp = icmp eq i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @nonexact_lshr_ne_last_zero(i8 %a) {
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; CHECK-LABEL: @nonexact_lshr_ne_last_zero(
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; CHECK-NEXT: ret i1 true
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;
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%shr = lshr i8 128, %a
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%cmp = icmp ne i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @nonexact_ashr_ne_last_zero(i8 %a) {
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; CHECK-LABEL: @nonexact_ashr_ne_last_zero(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr i8 -128, %a
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%cmp = icmp ne i8 %shr, 0
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ret i1 %cmp
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}
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define i1 @lshr_eq_first_zero(i8 %a) {
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; CHECK-LABEL: @lshr_eq_first_zero(
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; CHECK-NEXT: ret i1 false
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;
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%shr = lshr i8 0, %a
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%cmp = icmp eq i8 %shr, 2
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ret i1 %cmp
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}
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define i1 @ashr_eq_first_zero(i8 %a) {
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; CHECK-LABEL: @ashr_eq_first_zero(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr i8 0, %a
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%cmp = icmp eq i8 %shr, 2
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ret i1 %cmp
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}
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define i1 @lshr_ne_first_zero(i8 %a) {
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; CHECK-LABEL: @lshr_ne_first_zero(
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; CHECK-NEXT: ret i1 true
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;
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%shr = lshr i8 0, %a
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%cmp = icmp ne i8 %shr, 2
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ret i1 %cmp
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}
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define i1 @ashr_ne_first_zero(i8 %a) {
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; CHECK-LABEL: @ashr_ne_first_zero(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr i8 0, %a
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%cmp = icmp ne i8 %shr, 2
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ret i1 %cmp
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}
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define i1 @ashr_eq_both_minus1(i8 %a) {
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; CHECK-LABEL: @ashr_eq_both_minus1(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr i8 -1, %a
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%cmp = icmp eq i8 %shr, -1
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ret i1 %cmp
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}
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define i1 @ashr_ne_both_minus1(i8 %a) {
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; CHECK-LABEL: @ashr_ne_both_minus1(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr i8 -1, %a
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%cmp = icmp ne i8 %shr, -1
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ret i1 %cmp
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}
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define i1 @exact_ashr_eq_both_minus1(i8 %a) {
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; CHECK-LABEL: @exact_ashr_eq_both_minus1(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr exact i8 -1, %a
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%cmp = icmp eq i8 %shr, -1
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ret i1 %cmp
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}
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define i1 @exact_ashr_ne_both_minus1(i8 %a) {
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; CHECK-LABEL: @exact_ashr_ne_both_minus1(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr exact i8 -1, %a
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%cmp = icmp ne i8 %shr, -1
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ret i1 %cmp
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}
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define i1 @exact_ashr_eq_opposite_msb(i8 %a) {
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; CHECK-LABEL: @exact_ashr_eq_opposite_msb(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr exact i8 -128, %a
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%cmp = icmp eq i8 %shr, 1
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ret i1 %cmp
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}
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define i1 @exact_ashr_eq_noexactlog(i8 %a) {
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; CHECK-LABEL: @exact_ashr_eq_noexactlog(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr exact i8 -90, %a
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%cmp = icmp eq i8 %shr, -30
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ret i1 %cmp
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}
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define i1 @exact_ashr_ne_opposite_msb(i8 %a) {
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; CHECK-LABEL: @exact_ashr_ne_opposite_msb(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr exact i8 -128, %a
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%cmp = icmp ne i8 %shr, 1
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ret i1 %cmp
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}
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define i1 @ashr_eq_opposite_msb(i8 %a) {
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; CHECK-LABEL: @ashr_eq_opposite_msb(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr i8 -128, %a
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%cmp = icmp eq i8 %shr, 1
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ret i1 %cmp
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}
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define i1 @ashr_ne_opposite_msb(i8 %a) {
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; CHECK-LABEL: @ashr_ne_opposite_msb(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr i8 -128, %a
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%cmp = icmp ne i8 %shr, 1
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ret i1 %cmp
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}
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define i1 @exact_ashr_eq_shift_gt(i8 %a) {
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; CHECK-LABEL: @exact_ashr_eq_shift_gt(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr exact i8 -2, %a
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%cmp = icmp eq i8 %shr, -8
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ret i1 %cmp
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}
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define i1 @exact_ashr_ne_shift_gt(i8 %a) {
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; CHECK-LABEL: @exact_ashr_ne_shift_gt(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr exact i8 -2, %a
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%cmp = icmp ne i8 %shr, -8
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ret i1 %cmp
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}
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define i1 @nonexact_ashr_eq_shift_gt(i8 %a) {
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; CHECK-LABEL: @nonexact_ashr_eq_shift_gt(
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; CHECK-NEXT: ret i1 false
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;
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%shr = ashr i8 -2, %a
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%cmp = icmp eq i8 %shr, -8
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ret i1 %cmp
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}
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define i1 @nonexact_ashr_ne_shift_gt(i8 %a) {
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; CHECK-LABEL: @nonexact_ashr_ne_shift_gt(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr i8 -2, %a
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%cmp = icmp ne i8 %shr, -8
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ret i1 %cmp
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}
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define i1 @exact_lshr_eq_shift_gt(i8 %a) {
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; CHECK-LABEL: @exact_lshr_eq_shift_gt(
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; CHECK-NEXT: ret i1 false
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;
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%shr = lshr exact i8 2, %a
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%cmp = icmp eq i8 %shr, 8
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ret i1 %cmp
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}
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define i1 @exact_lshr_ne_shift_gt(i8 %a) {
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; CHECK-LABEL: @exact_lshr_ne_shift_gt(
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; CHECK-NEXT: ret i1 true
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;
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%shr = lshr exact i8 2, %a
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%cmp = icmp ne i8 %shr, 8
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ret i1 %cmp
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}
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define i1 @nonexact_lshr_eq_shift_gt(i8 %a) {
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; CHECK-LABEL: @nonexact_lshr_eq_shift_gt(
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; CHECK-NEXT: ret i1 false
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;
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%shr = lshr i8 2, %a
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%cmp = icmp eq i8 %shr, 8
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ret i1 %cmp
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}
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define i1 @nonexact_lshr_ne_shift_gt(i8 %a) {
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; CHECK-LABEL: @nonexact_lshr_ne_shift_gt(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr i8 2, %a
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%cmp = icmp ne i8 %shr, 8
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ret i1 %cmp
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}
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define i1 @exact_ashr_ne_noexactlog(i8 %a) {
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; CHECK-LABEL: @exact_ashr_ne_noexactlog(
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; CHECK-NEXT: ret i1 true
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;
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%shr = ashr exact i8 -90, %a
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%cmp = icmp ne i8 %shr, -30
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ret i1 %cmp
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}
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define i1 @exact_lshr_eq_noexactlog(i8 %a) {
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; CHECK-LABEL: @exact_lshr_eq_noexactlog(
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; CHECK-NEXT: ret i1 false
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;
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%shr = lshr exact i8 90, %a
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%cmp = icmp eq i8 %shr, 30
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ret i1 %cmp
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}
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define i1 @exact_lshr_ne_noexactlog(i8 %a) {
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; CHECK-LABEL: @exact_lshr_ne_noexactlog(
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; CHECK-NEXT: ret i1 true
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;
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%shr = lshr exact i8 90, %a
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%cmp = icmp ne i8 %shr, 30
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ret i1 %cmp
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}
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define i32 @exact_lshr_lowbit(i32 %shiftval) {
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; CHECK-LABEL: @exact_lshr_lowbit(
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; CHECK-NEXT: ret i32 7
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;
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%shr = lshr exact i32 7, %shiftval
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ret i32 %shr
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}
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define i32 @exact_ashr_lowbit(i32 %shiftval) {
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; CHECK-LABEL: @exact_ashr_lowbit(
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; CHECK-NEXT: ret i32 7
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;
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%shr = ashr exact i32 7, %shiftval
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ret i32 %shr
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}
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define i32 @ashr_zero(i32 %shiftval) {
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; CHECK-LABEL: @ashr_zero(
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; CHECK-NEXT: ret i32 0
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;
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%shr = ashr i32 0, %shiftval
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ret i32 %shr
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}
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define i257 @ashr_minus1(i257 %shiftval) {
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; CHECK-LABEL: @ashr_minus1(
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; CHECK-NEXT: ret i257 -1
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;
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%shr = ashr i257 -1, %shiftval
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ret i257 %shr
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}
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define <2 x i4097> @ashr_zero_vec(<2 x i4097> %shiftval) {
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; CHECK-LABEL: @ashr_zero_vec(
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; CHECK-NEXT: ret <2 x i4097> zeroinitializer
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;
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%shr = ashr <2 x i4097> zeroinitializer, %shiftval
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ret <2 x i4097> %shr
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}
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define <2 x i64> @ashr_minus1_vec(<2 x i64> %shiftval) {
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; CHECK-LABEL: @ashr_minus1_vec(
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; CHECK-NEXT: ret <2 x i64> <i64 -1, i64 -1>
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;
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%shr = ashr <2 x i64> <i64 -1, i64 -1>, %shiftval
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ret <2 x i64> %shr
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}
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define <2 x i4> @ashr_zero_minus1_vec(<2 x i4> %shiftval) {
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; CHECK-LABEL: @ashr_zero_minus1_vec(
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; CHECK-NEXT: ret <2 x i4> <i4 0, i4 -1>
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;
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%shr = ashr <2 x i4> <i4 0, i4 -1>, %shiftval
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ret <2 x i4> %shr
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}
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