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For some cases, InstCombine replaces the sequence of xor/sub instruction followed by cmp instruction into a single cmp instruction. However, this replacement may result suboptimal result especially when the xor/sub has more than one use, as discussed in bug 26465 (https://llvm.org/bugs/show_bug.cgi?id=26465). This patch make the replacement happen only when xor/sub has only one use. Differential Revision: http://reviews.llvm.org/D16915 Patch by Taewook Oh! llvm-svn: 260695
42 lines
1.1 KiB
LLVM
42 lines
1.1 KiB
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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;
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; This test makes sure that InstCombine does not replace the sequence of
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; xor/sub instruction followed by cmp instruction into a single cmp instruction
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; if there is more than one use of xor/sub.
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define zeroext i1 @test1(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: %xor = xor i32 %lhs, 5
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; CHECK-NEXT: %cmp1 = icmp eq i32 %xor, 10
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%xor = xor i32 %lhs, 5
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%cmp1 = icmp eq i32 %xor, 10
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%cmp2 = icmp eq i32 %xor, %rhs
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%sel = or i1 %cmp1, %cmp2
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ret i1 %sel
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}
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define zeroext i1 @test2(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: %xor = xor i32 %lhs, %rhs
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; CHECK-NEXT: %cmp1 = icmp eq i32 %xor, 0
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%xor = xor i32 %lhs, %rhs
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%cmp1 = icmp eq i32 %xor, 0
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%cmp2 = icmp eq i32 %xor, 32
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%sel = xor i1 %cmp1, %cmp2
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ret i1 %sel
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}
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define zeroext i1 @test3(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: %sub = sub nsw i32 %lhs, %rhs
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; CHECK-NEXT: %cmp1 = icmp eq i32 %sub, 0
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%sub = sub nsw i32 %lhs, %rhs
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%cmp1 = icmp eq i32 %sub, 0
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%cmp2 = icmp eq i32 %sub, 31
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%sel = or i1 %cmp1, %cmp2
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ret i1 %sel
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}
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