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277c5ff889
Summary: This intrinsic lets us set inactive lanes to an identity value when implementing wavefront reductions. In combination with Whole Wavefront Mode, it lets inactive lanes be skipped over as required by GLSL/Vulkan. Lowering the intrinsic needs to happen post-RA so that RA knows that the destination isn't completely overwritten due to the EXEC shenanigans, so we need another pseudo-instruction to represent the un-lowered intrinsic. Reviewers: tstellar, arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D34719 llvm-svn: 310088
30 lines
1.1 KiB
LLVM
30 lines
1.1 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
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; GCN-LABEL: {{^}}set_inactive:
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; GCN: s_not_b64 exec, exec
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; GCN: v_mov_b32_e32 {{v[0-9]+}}, 42
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; GCN: s_not_b64 exec, exec
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define amdgpu_kernel void @set_inactive(i32 addrspace(1)* %out, i32 %in) {
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%tmp = call i32 @llvm.amdgcn.set.inactive.i32(i32 %in, i32 42) #0
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store i32 %tmp, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}set_inactive_64:
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; GCN: s_not_b64 exec, exec
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; GCN: v_mov_b32_e32 {{v[0-9]+}}, 0
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; GCN: v_mov_b32_e32 {{v[0-9]+}}, 0
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; GCN: s_not_b64 exec, exec
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define amdgpu_kernel void @set_inactive_64(i64 addrspace(1)* %out, i64 %in) {
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%tmp = call i64 @llvm.amdgcn.set.inactive.i64(i64 %in, i64 0) #0
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store i64 %tmp, i64 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0
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declare i64 @llvm.amdgcn.set.inactive.i64(i64, i64) #0
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attributes #0 = { convergent readnone }
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