mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-22 20:43:44 +02:00
813af3fadc
This commit verifies that the parsed machine instructions contain the implicit register operands as specified by the MCInstrDesc. Variadic and call instructions aren't verified. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10781 llvm-svn: 241537
26 lines
486 B
YAML
26 lines
486 B
YAML
# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
|
|
# This test ensures that the MIR parser parses X86 machine instructions
|
|
# correctly.
|
|
|
|
--- |
|
|
|
|
define i32 @inc(i32 %a) {
|
|
entry:
|
|
%b = mul i32 %a, 11
|
|
ret i32 %b
|
|
}
|
|
|
|
...
|
|
---
|
|
# CHECK: name: inc
|
|
name: inc
|
|
body:
|
|
- id: 0
|
|
name: entry
|
|
instructions:
|
|
# CHECK: - MOV32rr
|
|
# CHECK-NEXT: - RETQ
|
|
- MOV32rr
|
|
- ' RETQ '
|
|
...
|