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813af3fadc
This commit verifies that the parsed machine instructions contain the implicit register operands as specified by the MCInstrDesc. Variadic and call instructions aren't verified. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10781 llvm-svn: 241537
41 lines
930 B
YAML
41 lines
930 B
YAML
# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
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# This test ensures that the MIR parser reports an error when an instruction
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# is missing one of its implicit register operands.
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--- |
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define i32 @foo(i32* %p) {
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entry:
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%a = load i32, i32* %p
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%0 = icmp sle i32 %a, 10
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br i1 %0, label %less, label %exit
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less:
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ret i32 0
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exit:
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ret i32 %a
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}
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...
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---
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name: foo
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body:
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- id: 0
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name: entry
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instructions:
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- '%eax = MOV32rm %rdi, 1, _, 0, _'
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- 'CMP32ri8 %eax, 10, implicit-def %eflags'
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# CHECK: [[@LINE+1]]:24: missing implicit register operand 'implicit %eflags'
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- 'JG_1 %bb.2.exit'
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- id: 1
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name: less
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instructions:
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- '%eax = MOV32r0 implicit-def %eflags'
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- id: 2
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name: exit
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instructions:
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- 'RETQ %eax'
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...
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