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421ddae8b6
ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010
77 lines
3.5 KiB
ArmAsm
77 lines
3.5 KiB
ArmAsm
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon,+fullfp16 -show-encoding < %s | FileCheck %s
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// Check that the assembler can handle the documented syntax for AArch64
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//------------------------------------------------------------------------------
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// Vector Integer Add
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//------------------------------------------------------------------------------
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add v0.8b, v1.8b, v2.8b
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add v0.16b, v1.16b, v2.16b
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add v0.4h, v1.4h, v2.4h
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add v0.8h, v1.8h, v2.8h
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add v0.2s, v1.2s, v2.2s
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add v0.4s, v1.4s, v2.4s
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add v0.2d, v1.2d, v2.2d
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// CHECK: add v0.8b, v1.8b, v2.8b // encoding: [0x20,0x84,0x22,0x0e]
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// CHECK: add v0.16b, v1.16b, v2.16b // encoding: [0x20,0x84,0x22,0x4e]
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// CHECK: add v0.4h, v1.4h, v2.4h // encoding: [0x20,0x84,0x62,0x0e]
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// CHECK: add v0.8h, v1.8h, v2.8h // encoding: [0x20,0x84,0x62,0x4e]
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// CHECK: add v0.2s, v1.2s, v2.2s // encoding: [0x20,0x84,0xa2,0x0e]
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// CHECK: add v0.4s, v1.4s, v2.4s // encoding: [0x20,0x84,0xa2,0x4e]
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// CHECK: add v0.2d, v1.2d, v2.2d // encoding: [0x20,0x84,0xe2,0x4e]
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//------------------------------------------------------------------------------
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// Vector Integer Sub
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//------------------------------------------------------------------------------
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sub v0.8b, v1.8b, v2.8b
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sub v0.16b, v1.16b, v2.16b
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sub v0.4h, v1.4h, v2.4h
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sub v0.8h, v1.8h, v2.8h
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sub v0.2s, v1.2s, v2.2s
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sub v0.4s, v1.4s, v2.4s
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sub v0.2d, v1.2d, v2.2d
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// CHECK: sub v0.8b, v1.8b, v2.8b // encoding: [0x20,0x84,0x22,0x2e]
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// CHECK: sub v0.16b, v1.16b, v2.16b // encoding: [0x20,0x84,0x22,0x6e]
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// CHECK: sub v0.4h, v1.4h, v2.4h // encoding: [0x20,0x84,0x62,0x2e]
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// CHECK: sub v0.8h, v1.8h, v2.8h // encoding: [0x20,0x84,0x62,0x6e]
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// CHECK: sub v0.2s, v1.2s, v2.2s // encoding: [0x20,0x84,0xa2,0x2e]
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// CHECK: sub v0.4s, v1.4s, v2.4s // encoding: [0x20,0x84,0xa2,0x6e]
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// CHECK: sub v0.2d, v1.2d, v2.2d // encoding: [0x20,0x84,0xe2,0x6e]
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//------------------------------------------------------------------------------
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// Vector Floating-Point Add
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//------------------------------------------------------------------------------
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fadd v0.4h, v1.4h, v2.4h
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fadd v0.8h, v1.8h, v2.8h
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fadd v0.2s, v1.2s, v2.2s
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fadd v0.4s, v1.4s, v2.4s
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fadd v0.2d, v1.2d, v2.2d
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// CHECK: fadd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x14,0x42,0x0e]
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// CHECK: fadd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0x42,0x4e]
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// CHECK: fadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0xd4,0x22,0x0e]
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// CHECK: fadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0xd4,0x22,0x4e]
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// CHECK: fadd v0.2d, v1.2d, v2.2d // encoding: [0x20,0xd4,0x62,0x4e]
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//------------------------------------------------------------------------------
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// Vector Floating-Point Sub
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//------------------------------------------------------------------------------
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fsub v0.4h, v1.4h, v2.4h
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fsub v0.8h, v1.8h, v2.8h
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fsub v0.2s, v1.2s, v2.2s
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fsub v0.4s, v1.4s, v2.4s
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fsub v0.2d, v1.2d, v2.2d
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// CHECK: fsub v0.4h, v1.4h, v2.4h // encoding: [0x20,0x14,0xc2,0x0e]
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// CHECK; fsub v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0xc2,0x4e]
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// CHECK: fsub v0.2s, v1.2s, v2.2s // encoding: [0x20,0xd4,0xa2,0x0e]
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// CHECK: fsub v0.4s, v1.4s, v2.4s // encoding: [0x20,0xd4,0xa2,0x4e]
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// CHECK: fsub v0.2d, v1.2d, v2.2d // encoding: [0x20,0xd4,0xe2,0x4e]
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