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llvm-mirror/test/CodeGen/MIR
History
Matt Arsenault 34dde63750 MIR: Fix missing serialization for HasTailCall
2021-03-21 13:14:04 -04:00
..
AArch64 [mir] Change 'undef' for MMO base addresses to 'unknown-address' 2021-03-10 16:46:44 -08:00
AMDGPU [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
ARM
Generic MIR: Fix missing serialization for HasTailCall 2021-03-21 13:14:04 -04:00
Hexagon
Mips
NVPTX
PowerPC
WebAssembly
X86 Reapply "[DebugInfo] Add new instruction and DIExpression operator for variadic debug values" 2021-03-05 12:32:05 +00:00
README

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.