mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
fedce4ad20
LSR prefers to schedule iv increments just before the latch. The recent 80511565 broadened this to moving increments in the original IR. This pointed out a robustness problem with the CGP transform. When we have a use of an induction increment outside of the loop (we canonicalize away from this form, but it happens e.g. unanalyzeable loops) we'd avoid performing the uadd/usub transform. Interestingly, all of these involve moving the increment closer to it's operands, so there's no concern about dominating all uses. We can handle that case cheaply, resulting in a more robust transform.
408 lines
16 KiB
LLVM
408 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=x86_64-linux -codegenprepare -S < %s | FileCheck %s
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define i32 @test_01(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: @test_01(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[MATH:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[IV]], i64 1)
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; CHECK-NEXT: [[MATH]] = extractvalue { i64, i1 } [[TMP0]], 0
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; CHECK-NEXT: [[OV:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
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; CHECK-NEXT: br i1 [[OV]], label [[EXIT:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[MATH]], 4
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[P:%.*]] to i8*
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; CHECK-NEXT: [[SUNKADDR1:%.*]] = getelementptr i8, i8* [[TMP1]], i64 [[SUNKADDR]]
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[SUNKADDR1]] to i32*
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; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[TMP2]] unordered, align 4
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; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
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; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 -1
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; CHECK: failure:
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; CHECK-NEXT: unreachable
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;
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entry:
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%scevgep = getelementptr i32, i32* %p, i64 -1
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
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%iv.next = add i64 %iv, -1
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%cond_1 = icmp eq i64 %iv, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%scevgep1 = getelementptr i32, i32* %scevgep, i64 %iv
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%loaded = load atomic i32, i32* %scevgep1 unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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; Similar to test_01, but with different offset.
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define i32 @test_01a(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: @test_01a(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[MATH:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[IV]], i64 1)
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; CHECK-NEXT: [[MATH]] = extractvalue { i64, i1 } [[TMP0]], 0
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; CHECK-NEXT: [[OV:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
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; CHECK-NEXT: br i1 [[OV]], label [[EXIT:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[MATH]], 4
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[P:%.*]] to i8*
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; CHECK-NEXT: [[SUNKADDR1:%.*]] = getelementptr i8, i8* [[TMP1]], i64 [[SUNKADDR]]
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; CHECK-NEXT: [[SUNKADDR2:%.*]] = getelementptr i8, i8* [[SUNKADDR1]], i64 -24
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[SUNKADDR2]] to i32*
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; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[TMP2]] unordered, align 4
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; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
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; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 -1
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; CHECK: failure:
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; CHECK-NEXT: unreachable
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;
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entry:
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%scevgep = getelementptr i32, i32* %p, i64 -7
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
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%iv.next = add i64 %iv, -1
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%cond_1 = icmp eq i64 %iv, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%scevgep1 = getelementptr i32, i32* %scevgep, i64 %iv
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%loaded = load atomic i32, i32* %scevgep1 unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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; TODO: We can use trick with usub here.
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define i32 @test_02(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: @test_02(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[MATH:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[IV]], i64 1)
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; CHECK-NEXT: [[MATH]] = extractvalue { i64, i1 } [[TMP0]], 0
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; CHECK-NEXT: [[OV:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
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; CHECK-NEXT: br i1 [[OV]], label [[EXIT:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[MATH]], 4
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[P:%.*]] to i8*
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; CHECK-NEXT: [[SUNKADDR1:%.*]] = getelementptr i8, i8* [[TMP1]], i64 [[SUNKADDR]]
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[SUNKADDR1]] to i32*
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; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[TMP2]] unordered, align 4
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; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
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; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 -1
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; CHECK: failure:
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; CHECK-NEXT: unreachable
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;
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entry:
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%scevgep = getelementptr i32, i32* %p, i64 -1
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
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%cond_1 = icmp eq i64 %iv, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%scevgep1 = getelementptr i32, i32* %scevgep, i64 %iv
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%loaded = load atomic i32, i32* %scevgep1 unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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%iv.next = add i64 %iv, -1
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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declare i1 @use(i64 %x)
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declare i1 @some_cond()
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; Make sure we do not move the increment below the point where it is used.
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define i32 @test_03_neg(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: @test_03_neg(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], -1
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; CHECK-NEXT: [[COND_0:%.*]] = call i1 @use(i64 [[IV_NEXT]])
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; CHECK-NEXT: br i1 [[COND_0]], label [[MIDDLE:%.*]], label [[FAILURE:%.*]]
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; CHECK: middle:
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; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[IV]], 0
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; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[IV_NEXT]], 4
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to i8*
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; CHECK-NEXT: [[SUNKADDR1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 [[SUNKADDR]]
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[SUNKADDR1]] to i32*
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; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[TMP1]] unordered, align 4
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; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
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; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 -1
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; CHECK: failure:
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; CHECK-NEXT: unreachable
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;
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entry:
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%scevgep = getelementptr i32, i32* %p, i64 -1
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
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%iv.next = add i64 %iv, -1
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%cond_0 = call i1 @use(i64 %iv.next)
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br i1 %cond_0, label %middle, label %failure
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middle:
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%cond_1 = icmp eq i64 %iv, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%scevgep1 = getelementptr i32, i32* %scevgep, i64 %iv
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%loaded = load atomic i32, i32* %scevgep1 unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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define i32 @test_04_neg(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: @test_04_neg(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: br label [[INNER:%.*]]
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; CHECK: inner:
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; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[IV]], 0
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; CHECK-NEXT: br i1 [[COND_1]], label [[INNER_BACKEDGE:%.*]], label [[EXIT:%.*]]
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; CHECK: inner_backedge:
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; CHECK-NEXT: [[COND_INNER:%.*]] = call i1 @some_cond()
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; CHECK-NEXT: br i1 [[COND_INNER]], label [[INNER]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[IV]], 4
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to i8*
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; CHECK-NEXT: [[SUNKADDR1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 [[SUNKADDR]]
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; CHECK-NEXT: [[SUNKADDR2:%.*]] = getelementptr i8, i8* [[SUNKADDR1]], i64 -4
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[SUNKADDR2]] to i32*
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; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[TMP1]] unordered, align 4
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; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], -1
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; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 -1
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; CHECK: failure:
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; CHECK-NEXT: unreachable
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;
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entry:
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%scevgep = getelementptr i32, i32* %p, i64 -1
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br label %loop
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loop:
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%iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
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br label %inner
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inner:
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%cond_1 = icmp eq i64 %iv, 0
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br i1 %cond_1, label %inner_backedge, label %exit
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inner_backedge:
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%cond_inner = call i1 @some_cond()
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br i1 %cond_inner, label %inner, label %backedge
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backedge:
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%scevgep1 = getelementptr i32, i32* %scevgep, i64 %iv
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%loaded = load atomic i32, i32* %scevgep1 unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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%iv.next = add i64 %iv, -1
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br i1 %cond_2, label %failure, label %loop
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exit:
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ret i32 -1
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failure:
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unreachable
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}
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; Here Cmp does not dominate latch.
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define i32 @test_05_neg(i32* %p, i64 %len, i32 %x, i1 %cond) {
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; CHECK-LABEL: @test_05_neg(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], -1
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; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_TRUE:%.*]], label [[BACKEDGE]]
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; CHECK: if.true:
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; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[IV]], 0
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; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[IV_NEXT]], 4
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to i8*
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; CHECK-NEXT: [[SUNKADDR1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 [[SUNKADDR]]
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[SUNKADDR1]] to i32*
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; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[TMP1]] unordered, align 4
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; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
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; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 -1
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; CHECK: failure:
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; CHECK-NEXT: unreachable
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;
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entry:
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%scevgep = getelementptr i32, i32* %p, i64 -1
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
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%iv.next = add i64 %iv, -1
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br i1 %cond, label %if.true, label %backedge
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if.true:
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%cond_1 = icmp eq i64 %iv, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%scevgep1 = getelementptr i32, i32* %scevgep, i64 %iv
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%loaded = load atomic i32, i32* %scevgep1 unordered, align 4
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit: ; preds = %loop
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ret i32 -1
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failure: ; preds = %backedge
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unreachable
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}
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; test_01, but with an additional use of %iv.next outside the loop
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define i32 @test_06(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: @test_06(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[MATH:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[IV]], i64 1)
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; CHECK-NEXT: [[MATH]] = extractvalue { i64, i1 } [[TMP0]], 0
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; CHECK-NEXT: [[OV:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
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; CHECK-NEXT: br i1 [[OV]], label [[EXIT:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[MATH]], 4
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[P:%.*]] to i8*
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; CHECK-NEXT: [[SUNKADDR1:%.*]] = getelementptr i8, i8* [[TMP1]], i64 [[SUNKADDR]]
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[SUNKADDR1]] to i32*
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; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[TMP2]] unordered, align 4
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; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
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; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 -1
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; CHECK: failure:
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; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[MATH]] to i32
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; CHECK-NEXT: ret i32 [[TRUNC]]
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;
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entry:
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%scevgep = getelementptr i32, i32* %p, i64 -1
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br label %loop
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loop: ; preds = %backedge, %entry
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%iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
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%cond_1 = icmp eq i64 %iv, 0
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br i1 %cond_1, label %exit, label %backedge
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backedge: ; preds = %loop
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%scevgep1 = getelementptr i32, i32* %scevgep, i64 %iv
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%loaded = load atomic i32, i32* %scevgep1 unordered, align 4
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%iv.next = add i64 %iv, -1
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%cond_2 = icmp eq i32 %loaded, %x
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br i1 %cond_2, label %failure, label %loop
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exit:
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ret i32 -1
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failure:
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%trunc = trunc i64 %iv.next to i32
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ret i32 %trunc
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}
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; Extra use outside loop which prevents us moving the increment to the cmp
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define i32 @test_07_neg(i32* %p, i64 %len, i32 %x) {
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; CHECK-LABEL: @test_07_neg(
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; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: br label [[LOOP:%.*]]
|
|
; CHECK: loop:
|
|
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ [[LEN:%.*]], [[ENTRY:%.*]] ]
|
|
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], -1
|
|
; CHECK-NEXT: [[SUNKADDR:%.*]] = mul i64 [[IV_NEXT]], 4
|
|
; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to i8*
|
|
; CHECK-NEXT: [[SUNKADDR1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 [[SUNKADDR]]
|
|
; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[SUNKADDR1]] to i32*
|
|
; CHECK-NEXT: [[LOADED:%.*]] = load atomic i32, i32* [[TMP1]] unordered, align 4
|
|
; CHECK-NEXT: [[COND_2:%.*]] = icmp eq i32 [[LOADED]], [[X:%.*]]
|
|
; CHECK-NEXT: br i1 [[COND_2]], label [[FAILURE:%.*]], label [[BACKEDGE]]
|
|
; CHECK: backedge:
|
|
; CHECK-NEXT: [[COND_1:%.*]] = icmp eq i64 [[IV]], 0
|
|
; CHECK-NEXT: br i1 [[COND_1]], label [[EXIT:%.*]], label [[LOOP]]
|
|
; CHECK: exit:
|
|
; CHECK-NEXT: ret i32 -1
|
|
; CHECK: failure:
|
|
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[IV_NEXT]] to i32
|
|
; CHECK-NEXT: ret i32 [[TRUNC]]
|
|
;
|
|
entry:
|
|
%scevgep = getelementptr i32, i32* %p, i64 -1
|
|
br label %loop
|
|
|
|
loop:
|
|
%iv = phi i64 [ %iv.next, %backedge ], [ %len, %entry ]
|
|
%iv.next = add i64 %iv, -1
|
|
%scevgep1 = getelementptr i32, i32* %scevgep, i64 %iv
|
|
%loaded = load atomic i32, i32* %scevgep1 unordered, align 4
|
|
%cond_2 = icmp eq i32 %loaded, %x
|
|
br i1 %cond_2, label %failure, label %backedge
|
|
|
|
backedge:
|
|
%cond_1 = icmp eq i64 %iv, 0
|
|
br i1 %cond_1, label %exit, label %loop
|
|
|
|
exit:
|
|
ret i32 -1
|
|
|
|
failure:
|
|
%trunc = trunc i64 %iv.next to i32
|
|
ret i32 %trunc
|
|
}
|