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08a3df5192
For now I have changed SimplifyDemandedBits and it's various callers to assume we know nothing for scalable vectors and to ignore the demanded bits completely. I have also done something similar for SimplifyDemandedVectorElts. These changes fix up lots of warnings due to calls to EVT::getVectorNumElements() for types with scalable vectors. These functions are all used for optimisations, rather than functional requirements. In future we can revisit this code if there is a need to improve code quality for SVE. Differential Revision: https://reviews.llvm.org/D80537
530 lines
17 KiB
C++
530 lines
17 KiB
C++
//===- llvm/unittest/CodeGen/AArch64SelectionDAGTest.cpp -------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Analysis/OptimizationRemarkEmitter.h"
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#include "llvm/AsmParser/Parser.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetMachine.h"
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#include "gtest/gtest.h"
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namespace llvm {
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class AArch64SelectionDAGTest : public testing::Test {
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protected:
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static void SetUpTestCase() {
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InitializeAllTargets();
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InitializeAllTargetMCs();
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}
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void SetUp() override {
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StringRef Assembly = "define void @f() { ret void }";
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Triple TargetTriple("aarch64--");
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std::string Error;
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const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
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// FIXME: These tests do not depend on AArch64 specifically, but we have to
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// initialize a target. A skeleton Target for unittests would allow us to
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// always run these tests.
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if (!T)
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return;
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TargetOptions Options;
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TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
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T->createTargetMachine("AArch64", "", "+sve", Options, None, None,
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CodeGenOpt::Aggressive)));
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if (!TM)
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return;
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SMDiagnostic SMError;
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M = parseAssemblyString(Assembly, SMError, Context);
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if (!M)
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report_fatal_error(SMError.getMessage());
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M->setDataLayout(TM->createDataLayout());
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F = M->getFunction("f");
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if (!F)
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report_fatal_error("F?");
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MachineModuleInfo MMI(TM.get());
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MF = std::make_unique<MachineFunction>(*F, *TM, *TM->getSubtargetImpl(*F), 0,
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MMI);
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DAG = std::make_unique<SelectionDAG>(*TM, CodeGenOpt::None);
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if (!DAG)
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report_fatal_error("DAG?");
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OptimizationRemarkEmitter ORE(F);
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DAG->init(*MF, ORE, nullptr, nullptr, nullptr, nullptr, nullptr);
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}
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TargetLoweringBase::LegalizeTypeAction getTypeAction(EVT VT) {
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return DAG->getTargetLoweringInfo().getTypeAction(Context, VT);
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}
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EVT getTypeToTransformTo(EVT VT) {
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return DAG->getTargetLoweringInfo().getTypeToTransformTo(Context, VT);
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}
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LLVMContext Context;
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std::unique_ptr<LLVMTargetMachine> TM;
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std::unique_ptr<Module> M;
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Function *F;
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std::unique_ptr<MachineFunction> MF;
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std::unique_ptr<SelectionDAG> DAG;
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};
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TEST_F(AArch64SelectionDAGTest, computeKnownBits_ZERO_EXTEND_VECTOR_INREG) {
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if (!TM)
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return;
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SDLoc Loc;
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auto Int8VT = EVT::getIntegerVT(Context, 8);
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auto Int16VT = EVT::getIntegerVT(Context, 16);
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auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4);
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auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2);
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auto InVec = DAG->getConstant(0, Loc, InVecVT);
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auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
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auto DemandedElts = APInt(2, 3);
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KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
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EXPECT_TRUE(Known.isZero());
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}
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TEST_F(AArch64SelectionDAGTest, computeKnownBitsSVE_ZERO_EXTEND_VECTOR_INREG) {
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if (!TM)
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return;
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SDLoc Loc;
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auto Int8VT = EVT::getIntegerVT(Context, 8);
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auto Int16VT = EVT::getIntegerVT(Context, 16);
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auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4, true);
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auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2, true);
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auto InVec = DAG->getConstant(0, Loc, InVecVT);
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auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
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auto DemandedElts = APInt(2, 3);
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KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
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// We don't know anything for SVE at the moment.
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EXPECT_EQ(Known.Zero, APInt(16, 0u));
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EXPECT_EQ(Known.One, APInt(16, 0u));
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EXPECT_FALSE(Known.isZero());
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}
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TEST_F(AArch64SelectionDAGTest, computeKnownBits_EXTRACT_SUBVECTOR) {
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if (!TM)
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return;
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto VecVT = EVT::getVectorVT(Context, IntVT, 3);
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auto IdxVT = EVT::getIntegerVT(Context, 64);
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auto Vec = DAG->getConstant(0, Loc, VecVT);
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auto ZeroIdx = DAG->getConstant(0, Loc, IdxVT);
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auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx);
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auto DemandedElts = APInt(3, 7);
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KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
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EXPECT_TRUE(Known.isZero());
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}
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TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_SIGN_EXTEND_VECTOR_INREG) {
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if (!TM)
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return;
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SDLoc Loc;
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auto Int8VT = EVT::getIntegerVT(Context, 8);
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auto Int16VT = EVT::getIntegerVT(Context, 16);
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auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4);
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auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2);
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auto InVec = DAG->getConstant(1, Loc, InVecVT);
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auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
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auto DemandedElts = APInt(2, 3);
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EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 15u);
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}
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TEST_F(AArch64SelectionDAGTest, ComputeNumSignBitsSVE_SIGN_EXTEND_VECTOR_INREG) {
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if (!TM)
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return;
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SDLoc Loc;
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auto Int8VT = EVT::getIntegerVT(Context, 8);
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auto Int16VT = EVT::getIntegerVT(Context, 16);
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auto InVecVT = EVT::getVectorVT(Context, Int8VT, 4, /*IsScalable=*/true);
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auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2, /*IsScalable=*/true);
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auto InVec = DAG->getConstant(1, Loc, InVecVT);
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auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
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auto DemandedElts = APInt(2, 3);
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EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 1u);
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}
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TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_EXTRACT_SUBVECTOR) {
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if (!TM)
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return;
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto VecVT = EVT::getVectorVT(Context, IntVT, 3);
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auto IdxVT = EVT::getIntegerVT(Context, 64);
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auto Vec = DAG->getConstant(1, Loc, VecVT);
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auto ZeroIdx = DAG->getConstant(0, Loc, IdxVT);
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auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx);
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auto DemandedElts = APInt(3, 7);
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EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 7u);
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}
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TEST_F(AArch64SelectionDAGTest, SimplifyDemandedVectorElts_EXTRACT_SUBVECTOR) {
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if (!TM)
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return;
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TargetLowering TL(*TM);
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto VecVT = EVT::getVectorVT(Context, IntVT, 3);
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auto IdxVT = EVT::getIntegerVT(Context, 64);
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auto Vec = DAG->getConstant(1, Loc, VecVT);
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auto ZeroIdx = DAG->getConstant(0, Loc, IdxVT);
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auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx);
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auto DemandedElts = APInt(3, 7);
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auto KnownUndef = APInt(3, 0);
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auto KnownZero = APInt(3, 0);
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TargetLowering::TargetLoweringOpt TLO(*DAG, false, false);
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EXPECT_EQ(TL.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef,
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KnownZero, TLO),
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false);
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}
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TEST_F(AArch64SelectionDAGTest, SimplifyDemandedBitsNEON) {
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if (!TM)
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return;
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TargetLowering TL(*TM);
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SDLoc Loc;
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auto Int8VT = EVT::getIntegerVT(Context, 8);
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auto InVecVT = EVT::getVectorVT(Context, Int8VT, 16);
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SDValue UnknownOp = DAG->getRegister(0, InVecVT);
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SDValue Mask1S = DAG->getConstant(0x8A, Loc, Int8VT);
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SDValue Mask1V = DAG->getSplatBuildVector(InVecVT, Loc, Mask1S);
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SDValue N0 = DAG->getNode(ISD::AND, Loc, InVecVT, Mask1V, UnknownOp);
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SDValue Mask2S = DAG->getConstant(0x55, Loc, Int8VT);
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SDValue Mask2V = DAG->getSplatBuildVector(InVecVT, Loc, Mask2S);
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SDValue Op = DAG->getNode(ISD::AND, Loc, InVecVT, N0, Mask2V);
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// N0 = ?000?0?0
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// Mask2V = 01010101
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// =>
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// Known.Zero = 00100000 (0xAA)
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KnownBits Known;
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APInt DemandedBits = APInt(8, 0xFF);
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TargetLowering::TargetLoweringOpt TLO(*DAG, false, false);
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EXPECT_TRUE(TL.SimplifyDemandedBits(Op, DemandedBits, Known, TLO));
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EXPECT_EQ(Known.Zero, APInt(8, 0xAA));
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}
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TEST_F(AArch64SelectionDAGTest, SimplifyDemandedBitsSVE) {
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if (!TM)
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return;
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TargetLowering TL(*TM);
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SDLoc Loc;
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auto Int8VT = EVT::getIntegerVT(Context, 8);
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auto InVecVT = EVT::getVectorVT(Context, Int8VT, 16, /*IsScalable=*/true);
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SDValue UnknownOp = DAG->getRegister(0, InVecVT);
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SDValue Mask1S = DAG->getConstant(0x8A, Loc, Int8VT);
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SDValue Mask1V = DAG->getSplatVector(InVecVT, Loc, Mask1S);
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SDValue N0 = DAG->getNode(ISD::AND, Loc, InVecVT, Mask1V, UnknownOp);
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SDValue Mask2S = DAG->getConstant(0x55, Loc, Int8VT);
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SDValue Mask2V = DAG->getSplatVector(InVecVT, Loc, Mask2S);
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SDValue Op = DAG->getNode(ISD::AND, Loc, InVecVT, N0, Mask2V);
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KnownBits Known;
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APInt DemandedBits = APInt(8, 0xFF);
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TargetLowering::TargetLoweringOpt TLO(*DAG, false, false);
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EXPECT_FALSE(TL.SimplifyDemandedBits(Op, DemandedBits, Known, TLO));
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EXPECT_EQ(Known.Zero, APInt(8, 0));
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}
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// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits.
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TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_ADD) {
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if (!TM)
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return;
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto UnknownOp = DAG->getRegister(0, IntVT);
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auto Mask = DAG->getConstant(0x8A, Loc, IntVT);
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auto N0 = DAG->getNode(ISD::AND, Loc, IntVT, Mask, UnknownOp);
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auto N1 = DAG->getConstant(0x55, Loc, IntVT);
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auto Op = DAG->getNode(ISD::ADD, Loc, IntVT, N0, N1);
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// N0 = ?000?0?0
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// N1 = 01010101
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// =>
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// Known.One = 01010101 (0x55)
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// Known.Zero = 00100000 (0x20)
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KnownBits Known = DAG->computeKnownBits(Op);
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EXPECT_EQ(Known.Zero, APInt(8, 0x20));
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EXPECT_EQ(Known.One, APInt(8, 0x55));
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}
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// Piggy-backing on the AArch64 tests to verify SelectionDAG::computeKnownBits.
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TEST_F(AArch64SelectionDAGTest, ComputeKnownBits_SUB) {
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if (!TM)
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return;
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto N0 = DAG->getConstant(0x55, Loc, IntVT);
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auto UnknownOp = DAG->getRegister(0, IntVT);
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auto Mask = DAG->getConstant(0x2e, Loc, IntVT);
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auto N1 = DAG->getNode(ISD::AND, Loc, IntVT, Mask, UnknownOp);
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auto Op = DAG->getNode(ISD::SUB, Loc, IntVT, N0, N1);
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// N0 = 01010101
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// N1 = 00?0???0
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// =>
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// Known.One = 00000001 (0x1)
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// Known.Zero = 10000000 (0x80)
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KnownBits Known = DAG->computeKnownBits(Op);
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EXPECT_EQ(Known.Zero, APInt(8, 0x80));
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EXPECT_EQ(Known.One, APInt(8, 0x1));
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}
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TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_BUILD_VECTOR) {
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if (!TM)
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return;
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TargetLowering TL(*TM);
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto VecVT = EVT::getVectorVT(Context, IntVT, 16, false);
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// Create a BUILD_VECTOR
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SDValue Op = DAG->getConstant(1, Loc, VecVT);
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EXPECT_EQ(Op->getOpcode(), ISD::BUILD_VECTOR);
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EXPECT_TRUE(DAG->isSplatValue(Op, /*AllowUndefs=*/false));
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APInt UndefElts;
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APInt DemandedElts;
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EXPECT_FALSE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
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// Width=16, Mask=3
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DemandedElts = APInt(16, 3);
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EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
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}
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TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_ADD_of_BUILD_VECTOR) {
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if (!TM)
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return;
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TargetLowering TL(*TM);
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto VecVT = EVT::getVectorVT(Context, IntVT, 16, false);
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// Should create BUILD_VECTORs
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SDValue Val1 = DAG->getConstant(1, Loc, VecVT);
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SDValue Val2 = DAG->getConstant(3, Loc, VecVT);
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EXPECT_EQ(Val1->getOpcode(), ISD::BUILD_VECTOR);
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SDValue Op = DAG->getNode(ISD::ADD, Loc, VecVT, Val1, Val2);
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EXPECT_TRUE(DAG->isSplatValue(Op, /*AllowUndefs=*/false));
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APInt UndefElts;
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APInt DemandedElts;
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EXPECT_FALSE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
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// Width=16, Mask=3
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DemandedElts = APInt(16, 3);
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EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
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}
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TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_SPLAT_VECTOR) {
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if (!TM)
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return;
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TargetLowering TL(*TM);
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto VecVT = EVT::getVectorVT(Context, IntVT, 16, true);
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// Create a SPLAT_VECTOR
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SDValue Op = DAG->getConstant(1, Loc, VecVT);
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EXPECT_EQ(Op->getOpcode(), ISD::SPLAT_VECTOR);
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EXPECT_TRUE(DAG->isSplatValue(Op, /*AllowUndefs=*/false));
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APInt UndefElts;
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APInt DemandedElts;
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EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
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// Width=16, Mask=3. These bits should be ignored.
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DemandedElts = APInt(16, 3);
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EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
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}
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TEST_F(AArch64SelectionDAGTest, isSplatValue_Scalable_ADD_of_SPLAT_VECTOR) {
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if (!TM)
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return;
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TargetLowering TL(*TM);
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto VecVT = EVT::getVectorVT(Context, IntVT, 16, true);
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// Should create SPLAT_VECTORS
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SDValue Val1 = DAG->getConstant(1, Loc, VecVT);
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SDValue Val2 = DAG->getConstant(3, Loc, VecVT);
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EXPECT_EQ(Val1->getOpcode(), ISD::SPLAT_VECTOR);
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SDValue Op = DAG->getNode(ISD::ADD, Loc, VecVT, Val1, Val2);
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EXPECT_TRUE(DAG->isSplatValue(Op, /*AllowUndefs=*/false));
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APInt UndefElts;
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APInt DemandedElts;
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EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
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// Width=16, Mask=3. These bits should be ignored.
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DemandedElts = APInt(16, 3);
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EXPECT_TRUE(DAG->isSplatValue(Op, DemandedElts, UndefElts));
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}
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TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Fixed_BUILD_VECTOR) {
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if (!TM)
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return;
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TargetLowering TL(*TM);
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto VecVT = EVT::getVectorVT(Context, IntVT, 16, false);
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// Create a BUILD_VECTOR
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SDValue Op = DAG->getConstant(1, Loc, VecVT);
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EXPECT_EQ(Op->getOpcode(), ISD::BUILD_VECTOR);
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int SplatIdx = -1;
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EXPECT_EQ(DAG->getSplatSourceVector(Op, SplatIdx), Op);
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EXPECT_EQ(SplatIdx, 0);
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}
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TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Fixed_ADD_of_BUILD_VECTOR) {
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if (!TM)
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return;
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TargetLowering TL(*TM);
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto VecVT = EVT::getVectorVT(Context, IntVT, 16, false);
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// Should create BUILD_VECTORs
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SDValue Val1 = DAG->getConstant(1, Loc, VecVT);
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SDValue Val2 = DAG->getConstant(3, Loc, VecVT);
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EXPECT_EQ(Val1->getOpcode(), ISD::BUILD_VECTOR);
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SDValue Op = DAG->getNode(ISD::ADD, Loc, VecVT, Val1, Val2);
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|
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int SplatIdx = -1;
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EXPECT_EQ(DAG->getSplatSourceVector(Op, SplatIdx), Op);
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EXPECT_EQ(SplatIdx, 0);
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}
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|
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TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Scalable_SPLAT_VECTOR) {
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if (!TM)
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return;
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|
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TargetLowering TL(*TM);
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|
|
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SDLoc Loc;
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auto IntVT = EVT::getIntegerVT(Context, 8);
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auto VecVT = EVT::getVectorVT(Context, IntVT, 16, true);
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// Create a SPLAT_VECTOR
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SDValue Op = DAG->getConstant(1, Loc, VecVT);
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EXPECT_EQ(Op->getOpcode(), ISD::SPLAT_VECTOR);
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|
|
|
int SplatIdx = -1;
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EXPECT_EQ(DAG->getSplatSourceVector(Op, SplatIdx), Op);
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|
EXPECT_EQ(SplatIdx, 0);
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|
}
|
|
|
|
TEST_F(AArch64SelectionDAGTest, getSplatSourceVector_Scalable_ADD_of_SPLAT_VECTOR) {
|
|
if (!TM)
|
|
return;
|
|
|
|
TargetLowering TL(*TM);
|
|
|
|
SDLoc Loc;
|
|
auto IntVT = EVT::getIntegerVT(Context, 8);
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|
auto VecVT = EVT::getVectorVT(Context, IntVT, 16, true);
|
|
|
|
// Should create SPLAT_VECTORS
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|
SDValue Val1 = DAG->getConstant(1, Loc, VecVT);
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|
SDValue Val2 = DAG->getConstant(3, Loc, VecVT);
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|
EXPECT_EQ(Val1->getOpcode(), ISD::SPLAT_VECTOR);
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|
SDValue Op = DAG->getNode(ISD::ADD, Loc, VecVT, Val1, Val2);
|
|
|
|
int SplatIdx = -1;
|
|
EXPECT_EQ(DAG->getSplatSourceVector(Op, SplatIdx), Op);
|
|
EXPECT_EQ(SplatIdx, 0);
|
|
}
|
|
|
|
TEST_F(AArch64SelectionDAGTest, getTypeConversion_SplitScalableMVT) {
|
|
if (!TM)
|
|
return;
|
|
|
|
MVT VT = MVT::nxv4i64;
|
|
EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypeSplitVector);
|
|
ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
|
|
}
|
|
|
|
TEST_F(AArch64SelectionDAGTest, getTypeConversion_PromoteScalableMVT) {
|
|
if (!TM)
|
|
return;
|
|
|
|
MVT VT = MVT::nxv2i32;
|
|
EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypePromoteInteger);
|
|
ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
|
|
}
|
|
|
|
TEST_F(AArch64SelectionDAGTest, getTypeConversion_NoScalarizeMVT_nxv1f32) {
|
|
if (!TM)
|
|
return;
|
|
|
|
MVT VT = MVT::nxv1f32;
|
|
EXPECT_NE(getTypeAction(VT), TargetLoweringBase::TypeScalarizeVector);
|
|
ASSERT_TRUE(getTypeToTransformTo(VT).isScalableVector());
|
|
}
|
|
|
|
TEST_F(AArch64SelectionDAGTest, getTypeConversion_SplitScalableEVT) {
|
|
if (!TM)
|
|
return;
|
|
|
|
EVT VT = EVT::getVectorVT(Context, MVT::i64, 256, true);
|
|
EXPECT_EQ(getTypeAction(VT), TargetLoweringBase::TypeSplitVector);
|
|
EXPECT_EQ(getTypeToTransformTo(VT), VT.getHalfNumVectorElementsVT(Context));
|
|
}
|
|
|
|
TEST_F(AArch64SelectionDAGTest, getTypeConversion_WidenScalableEVT) {
|
|
if (!TM)
|
|
return;
|
|
|
|
EVT FromVT = EVT::getVectorVT(Context, MVT::i64, 6, true);
|
|
EVT ToVT = EVT::getVectorVT(Context, MVT::i64, 8, true);
|
|
|
|
EXPECT_EQ(getTypeAction(FromVT), TargetLoweringBase::TypeWidenVector);
|
|
EXPECT_EQ(getTypeToTransformTo(FromVT), ToVT);
|
|
}
|
|
|
|
TEST_F(AArch64SelectionDAGTest, getTypeConversion_NoScalarizeEVT_nxv1f128) {
|
|
if (!TM)
|
|
return;
|
|
|
|
EVT FromVT = EVT::getVectorVT(Context, MVT::f128, 1, true);
|
|
EXPECT_DEATH(getTypeAction(FromVT), "Cannot legalize this vector");
|
|
}
|
|
|
|
} // end namespace llvm
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