Craig Topper bea426ec19 [RISCV] Add RISCVISD::BR_CC similar to RISCVISD::SELECT_CC. ... This allows me to introduce similar combines for branches as we have recently added for SELECT_CC. Some of them are less useful for standalone setccs and only help branch instructions. By having a BR_CC node its easier to only affect branches. I'm using CondCodeSDNode to make isel patterns easier to write so we can refer to the codes by name. SELECT_CC uses a constant instead. I've translated the condition code just like SELECT_CC so we need less patterns for the swapped conditions. This includes special cases for X < 1 and X > -1 that get translated to blez and bgez by using a 0 constant. computeKnownBitsForTargetNode support for SELECT_CC is added to allow MaskedValueIsZero to work for cases where the true and false values of the SELECT_CC are setccs and the result of the SELECT_CC is used by a BR_CC. This was needed to avoid regressions in some of the overflow tests. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D98159		2021-03-15 11:54:01 -07:00
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AArch64	[AArch64] Implement __rndr, __rndrrs intrinsics	2021-03-15 17:51:48 +00:00
AMDGPU	[amdgpu] Implement lower function LDS pass	2021-03-15 15:24:01 +00:00
ARC
ARM
AVR
BPF
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Hexagon
Inputs
Lanai
M68k
Mips
MIR
MSP430
NVPTX
PowerPC	[NFC][PowerPC] Add additional load/store test cases	2021-03-15 08:54:38 -05:00
RISCV	[RISCV] Add RISCVISD::BR_CC similar to RISCVISD::SELECT_CC.	2021-03-15 11:54:01 -07:00
SPARC
SystemZ
Thumb
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VE
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X86	[X86][SSE] isHorizontalBinOp - ensure we clear any unused source operands to improve HADD/SUB matching	2021-03-15 16:24:29 +00:00
XCore