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- `llvm.amdgcn.endpgm` is added to enable "abort" support. Differential Revision: https://reviews.llvm.org/D90809
51 lines
1.3 KiB
LLVM
51 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
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define amdgpu_kernel void @test0() {
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; CHECK-LABEL: test0:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_endpgm
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tail call void @llvm.amdgcn.endpgm()
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unreachable
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}
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define void @test1() {
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; CHECK-LABEL: test1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_endpgm
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tail call void @llvm.amdgcn.endpgm()
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unreachable
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}
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define amdgpu_kernel void @test2(i32* %p, i32 %x) {
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; CHECK-LABEL: test2:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_load_dword s2, s[0:1], 0x2c
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_cmp_lt_i32 s2, 1
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; CHECK-NEXT: s_cbranch_scc0 BB2_2
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; CHECK-NEXT: ; %bb.1: ; %else
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; CHECK-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; CHECK-NEXT: v_mov_b32_e32 v2, s2
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: v_mov_b32_e32 v1, s1
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; CHECK-NEXT: flat_store_dword v[0:1], v2
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: BB2_2: ; %then
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; CHECK-NEXT: s_endpgm
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%cond = icmp sgt i32 %x, 0
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br i1 %cond, label %then, label %else
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then:
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tail call void @llvm.amdgcn.endpgm()
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unreachable
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else:
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store i32 %x, i32* %p
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ret void
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}
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declare void @llvm.amdgcn.endpgm()
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