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llvm-mirror/test/CodeGen/AMDGPU/dce-disjoint-intervals.mir
Matt Arsenault a8a00a4e2a AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
SGPR_128 only includes the real allocatable SGPRs, and SReg_128 adds
the additional non-allocatable TTMP registers. There's no point in
allocating SReg_128 vregs. This shrinks the size of the classes
regalloc needs to consider, which is usually good.

llvm-svn: 374284
2019-10-10 07:11:33 +00:00

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# RUN: llc -mtriple=amdgcn-- -run-pass=liveintervals,dead-mi-elimination,simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# This is used to fail verififcation if MachineDCE tracks LIS.
# GCN-LABEL: name: foo
# GCN: S_ENDPGM
---
name: foo
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
%10:sgpr_128 = S_LOAD_DWORDX4_IMM killed $noreg, 9, 0, 0
S_NOP 0, implicit-def %4:sgpr_128, implicit %10.sub1:sgpr_128
S_CBRANCH_SCC0 %bb.3, implicit undef $scc
S_BRANCH %bb.1
bb.1:
S_CBRANCH_SCC0 %bb.2, implicit undef $scc
S_BRANCH %bb.3
bb.2:
%8:sreg_32_xm0 = COPY %4.sub1:sgpr_128
%7:sreg_32_xm0 = COPY %10.sub1:sgpr_128
S_BRANCH %bb.4
bb.3:
%10:sgpr_128 = S_LOAD_DWORDX4_IMM killed $noreg, 10, 0, 0
%7:sreg_32_xm0 = COPY %10.sub1:sgpr_128
%8:sreg_32_xm0 = COPY %10.sub2:sgpr_128
bb.4:
S_NOP 0, implicit %10
$sgpr0 = COPY %8:sreg_32_xm0
$sgpr1 = COPY %7:sreg_32_xm0
S_ENDPGM 0, implicit $sgpr0, implicit $sgpr1
...