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https://github.com/RPCS3/llvm-mirror.git
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d8fddd2027
Enabled "bound_ctrl:1" and disabled "bound_ctrl:-1" syntax. Corrected printer to output "bound_ctrl:1" instead of "bound_ctrl:0". See bug 35397 for detailed issue description. Differential Revision: https://reviews.llvm.org/D97048
75 lines
3.6 KiB
LLVM
75 lines
3.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP64,GFX90A
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,DPP32,GFX10
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; GCN-LABEL: {{^}}dpp64_ceil:
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; GCN: global_load_dwordx2 [[V:v\[[0-9:]+\]]],
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; DPP64: v_ceil_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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define amdgpu_kernel void @dpp64_ceil(i64 addrspace(1)* %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
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%load = load i64, i64 addrspace(1)* %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%round = tail call double @llvm.ceil.f64(double %tmp1)
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%tmp2 = bitcast double %round to i64
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store i64 %tmp2, i64 addrspace(1)* %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp64_rcp:
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; GCN: global_load_dwordx2 [[V:v\[[0-9:]+\]]],
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; DPP64: v_rcp_f64_dpp [[V]], [[V]] row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; DPP32-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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define amdgpu_kernel void @dpp64_rcp(i64 addrspace(1)* %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
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%load = load i64, i64 addrspace(1)* %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%rcp = call double @llvm.amdgcn.rcp.f64(double %tmp1)
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%tmp2 = bitcast double %rcp to i64
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store i64 %tmp2, i64 addrspace(1)* %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp64_rcp_unsupported_ctl:
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; GCN-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; GCN: v_rcp_f64_e32
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define amdgpu_kernel void @dpp64_rcp_unsupported_ctl(i64 addrspace(1)* %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
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%load = load i64, i64 addrspace(1)* %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%rcp = fdiv fast double 1.0, %tmp1
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%tmp2 = bitcast double %rcp to i64
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store i64 %tmp2, i64 addrspace(1)* %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp64_div:
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; GCN: global_load_dwordx2 [[V:v\[[0-9:]+\]]],
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; GFX90A-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_newbcast:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; GFX10-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} row_share:1 row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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; GCN: v_div_scale_f64
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; GCN: v_rcp_f64_e32
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define amdgpu_kernel void @dpp64_div(i64 addrspace(1)* %arg, i64 %in1) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id
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%load = load i64, i64 addrspace(1)* %gep
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%tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 337, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i64 %tmp0 to double
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%rcp = fdiv double 15.0, %tmp1
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%tmp2 = bitcast double %rcp to i64
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store i64 %tmp2, i64 addrspace(1)* %gep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare i64 @llvm.amdgcn.update.dpp.i64(i64, i64, i32, i32, i32, i1) #0
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declare double @llvm.ceil.f64(double)
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declare double @llvm.amdgcn.rcp.f64(double)
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attributes #0 = { nounwind readnone convergent }
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