mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
c9407d40f8
The operand value was always 1 (except in some bad MIR tests) so it was redundant. Differential Revision: https://reviews.llvm.org/D90378
681 lines
16 KiB
YAML
681 lines
16 KiB
YAML
# RUN: llc -march=amdgcn -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s
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# GCN-LABEL: name: merge-m0-many-init
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# GCN: bb.0.entry:
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 65536
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 65536
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.1:
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.2:
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# GCN: SI_INIT_M0 65536
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.3:
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# GCN: SI_INIT_M0 3
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# GCN: bb.4:
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# GCN-NOT: SI_INIT_M0
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# GCN: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 4
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.5:
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# GCN-NOT: SI_INIT_M0
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# GCN: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 4
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.6:
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# GCN: SI_INIT_M0 -1,
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# GCN-NEXT: DS_WRITE_B32
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# GCN: SI_INIT_M0 %2
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 %2
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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---
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name: merge-m0-many-init
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: sreg_32_xm0 }
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body: |
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bb.0.entry:
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successors: %bb.1, %bb.2
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.2
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.4, %bb.5
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S_CBRANCH_VCCZ %bb.4, implicit undef $vcc
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S_BRANCH %bb.5
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bb.4:
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successors: %bb.6
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SI_INIT_M0 3, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 4, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.6
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bb.5:
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successors: %bb.6
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SI_INIT_M0 3, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 4, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.6
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bb.6:
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successors: %bb.0.entry, %bb.6
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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%2 = IMPLICIT_DEF
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SI_INIT_M0 %2, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 %2, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_CBRANCH_VCCZ %bb.6, implicit undef $vcc
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S_BRANCH %bb.0.entry
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...
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# GCN-LABEL: name: merge-m0-dont-hoist-past-init-with-different-initializer
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# GCN: bb.0.entry:
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# GCN: SI_INIT_M0 65536
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.1:
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# GCN-NOT: SI_INIT_M0 65536
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# GCN-NOT: SI_INIT_M0 -1
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# GCN: bb.2:
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# GCN: SI_INIT_M0 -1
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# GCN: bb.3:
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# GCN: SI_INIT_M0 -1
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---
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name: merge-m0-dont-hoist-past-init-with-different-initializer
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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body: |
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bb.0.entry:
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successors: %bb.1
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.2, %bb.3
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_CBRANCH_VCCZ %bb.2, implicit undef $vcc
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S_BRANCH %bb.3
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bb.2:
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successors: %bb.4
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.4
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bb.3:
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successors: %bb.4
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.4
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bb.4:
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S_ENDPGM 0
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...
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# GCN-LABEL: name: merge-m0-after-prologue
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# GCN: bb.0.entry:
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# GCN-NOT: SI_INIT_M0
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# GCN: S_OR_B64
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# GCN-NEXT: SI_INIT_M0
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# GCN: bb.1:
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# GCN-NOT: SI_INIT_M0 -1
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# GCN: bb.2:
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# GCN-NOT: SI_INIT_MO -1
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---
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name: merge-m0-after-prologue
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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body: |
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bb.0.entry:
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successors: %bb.1, %bb.2
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liveins: $sgpr0_sgpr1
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$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.3
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.3
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bb.2:
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successors: %bb.3
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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S_ENDPGM 0
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...
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# GCN-LABEL: name: move-m0-avoid-hazard
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# GCN: $m0 = S_MOV_B32 -1
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# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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---
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name: move-m0-avoid-hazard
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body: |
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bb.0:
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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$m0 = S_MOV_B32 -1
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DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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...
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# GCN-LABEL: name: move-m0-with-prologue
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# GCN: $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
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# GCN: $m0 = S_MOV_B32 -1
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# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
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# GCN-NEXT: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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---
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name: move-m0-with-prologue
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
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$vgpr0 = V_MOV_B32_e32 0, implicit $exec
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$m0 = S_MOV_B32 -1
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DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
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...
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# GCN-LABEL: name: move-m0-different-initializer
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: %0:vgpr_32 = IMPLICIT_DEF
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# GCN: SI_INIT_M0 65536
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# GCN-NEXT: S_NOP
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---
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name: move-m0-different-initializer
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_NOP 0
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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...
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# GCN-LABEL: name: move-m0-schedule-boundary
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# GCN: S_SETREG
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# GCN-NEXT: SI_INIT_M0 -1
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---
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name: move-m0-schedule-boundary
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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body: |
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bb.0:
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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...
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# GCN-LABEL: name: m0-in-loop-0
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# GCN: bb.0.entry:
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.1:
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: $m0 = COPY %2
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---
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name: m0-in-loop-0
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: sgpr_32 }
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body: |
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bb.0.entry:
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successors: %bb.1
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.1, %bb.2
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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$m0 = COPY %2:sgpr_32
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S_SENDMSG 34, implicit $exec, implicit $m0
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S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN-LABEL: name: m0-in-loop-1
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# GCN: bb.0.entry:
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.1:
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# GCN-NOT: SI_INIT_M0 -1
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# GCN: DS_WRITE_B32
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---
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name: m0-in-loop-1
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: sgpr_32 }
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body: |
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bb.0.entry:
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successors: %bb.1
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.1, %bb.2
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN-LABEL: name: m0-in-loop-2
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# GCN: bb.0.entry:
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.1:
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# GCN: $m0 = COPY %2
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# GCN-NEXT: SENDMSG
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# GCN-NEXT: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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|
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---
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name: m0-in-loop-2
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: sgpr_32 }
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body: |
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bb.0.entry:
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successors: %bb.1
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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%2 = IMPLICIT_DEF
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.1, %bb.2
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$m0 = COPY %2:sgpr_32
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S_SENDMSG 34, implicit $exec, implicit $m0
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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# GCN-LABEL: name: m0-in-loop-3
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# GCN: bb.0.entry:
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: IMPLICIT_DEF
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.1:
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# GCN: $m0 = COPY %2
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# GCN-NEXT: SENDMSG
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# GCN-NEXT: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: DS_WRITE_B32
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|
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---
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name: m0-in-loop-3
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: sgpr_32 }
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body: |
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|
bb.0.entry:
|
|
successors: %bb.1
|
|
|
|
%0 = IMPLICIT_DEF
|
|
%1 = IMPLICIT_DEF
|
|
%2 = IMPLICIT_DEF
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
successors: %bb.1, %bb.2
|
|
|
|
$m0 = COPY %2:sgpr_32
|
|
S_SENDMSG 34, implicit $exec, implicit $m0
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
|
|
S_BRANCH %bb.2
|
|
|
|
bb.2:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: m0-in-loop-4
|
|
# GCN: bb.0.entry:
|
|
# GCN: SI_INIT_M0 -1
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
|
|
# GCN: bb.1:
|
|
# GCN: SI_INIT_M0 -1
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
# GCN-NEXT: $m0 = COPY %2
|
|
# GCN-NEXT: SENDMSG
|
|
|
|
---
|
|
name: m0-in-loop-4
|
|
registers:
|
|
- { id: 0, class: vgpr_32 }
|
|
- { id: 1, class: vgpr_32 }
|
|
- { id: 2, class: sgpr_32 }
|
|
body: |
|
|
bb.0.entry:
|
|
successors: %bb.1
|
|
|
|
%0 = IMPLICIT_DEF
|
|
%1 = IMPLICIT_DEF
|
|
%2 = IMPLICIT_DEF
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
successors: %bb.1, %bb.2
|
|
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
$m0 = COPY %2:sgpr_32
|
|
S_SENDMSG 34, implicit $exec, implicit $m0
|
|
S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
|
|
S_BRANCH %bb.2
|
|
|
|
bb.2:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: m0-in-loop-5
|
|
# GCN: bb.0.entry:
|
|
# GCN: SI_INIT_M0 -1
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
|
|
# GCN: bb.1:
|
|
# GCN: SI_INIT_M0 65536
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
# GCN-NEXT: SI_INIT_M0 -1
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
# GCN-NEXT: $m0 = COPY %2
|
|
# GCN-NEXT: SENDMSG
|
|
|
|
---
|
|
name: m0-in-loop-5
|
|
registers:
|
|
- { id: 0, class: vgpr_32 }
|
|
- { id: 1, class: vgpr_32 }
|
|
- { id: 2, class: sgpr_32 }
|
|
body: |
|
|
bb.0.entry:
|
|
successors: %bb.1
|
|
|
|
%0 = IMPLICIT_DEF
|
|
%1 = IMPLICIT_DEF
|
|
%2 = IMPLICIT_DEF
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
successors: %bb.1, %bb.2
|
|
|
|
SI_INIT_M0 65536, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
$m0 = COPY %2:sgpr_32
|
|
S_SENDMSG 34, implicit $exec, implicit $m0
|
|
S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
|
|
S_BRANCH %bb.2
|
|
|
|
bb.2:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: m0-in-loop-6
|
|
# GCN: bb.0.entry:
|
|
# GCN: SI_INIT_M0 -1
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
|
|
# GCN: bb.1:
|
|
# GCN: SI_INIT_M0 -1
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
# GCN-NEXT: $m0 = COPY %2
|
|
# GCN-NEXT: SENDMSG
|
|
|
|
---
|
|
name: m0-in-loop-6
|
|
registers:
|
|
- { id: 0, class: vgpr_32 }
|
|
- { id: 1, class: vgpr_32 }
|
|
- { id: 2, class: sgpr_32 }
|
|
body: |
|
|
bb.0.entry:
|
|
successors: %bb.1
|
|
|
|
%0 = IMPLICIT_DEF
|
|
%1 = IMPLICIT_DEF
|
|
%2 = IMPLICIT_DEF
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
successors: %bb.2
|
|
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
$m0 = COPY %2:sgpr_32
|
|
S_SENDMSG 34, implicit $exec, implicit $m0
|
|
S_BRANCH %bb.2
|
|
|
|
bb.2:
|
|
successors: %bb.3, %bb.1
|
|
S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
|
|
S_BRANCH %bb.3
|
|
|
|
|
|
bb.3:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
# GCN-LABEL: name: m0-in-loop-7
|
|
# GCN: bb.0.entry:
|
|
# GCN: SI_INIT_M0 -1
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: IMPLICIT_DEF
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
|
|
# GCN: bb.1:
|
|
# GCN: SI_INIT_M0 -1
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
# GCN-NEXT: DS_WRITE_B32
|
|
|
|
# GCN: bb.2:
|
|
# GCN: $m0 = COPY %2
|
|
# GCN-NEXT: SENDMSG
|
|
|
|
---
|
|
name: m0-in-loop-7
|
|
registers:
|
|
- { id: 0, class: vgpr_32 }
|
|
- { id: 1, class: vgpr_32 }
|
|
- { id: 2, class: sgpr_32 }
|
|
body: |
|
|
bb.0.entry:
|
|
successors: %bb.1
|
|
|
|
%0 = IMPLICIT_DEF
|
|
%1 = IMPLICIT_DEF
|
|
%2 = IMPLICIT_DEF
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
S_BRANCH %bb.1
|
|
|
|
bb.1:
|
|
successors: %bb.2
|
|
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
SI_INIT_M0 -1, implicit-def $m0
|
|
DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
|
|
S_BRANCH %bb.2
|
|
|
|
bb.2:
|
|
successors: %bb.3, %bb.1
|
|
$m0 = COPY %2:sgpr_32
|
|
S_SENDMSG 34, implicit $exec, implicit $m0
|
|
S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
|
|
S_BRANCH %bb.3
|
|
|
|
bb.3:
|
|
S_ENDPGM 0
|
|
...
|