mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
e8b8eaa4d0
There are a number of MIR tests using instructions on subtargets where they don't really exist. These are some of the easy cases that don't require splitting up test functions.
109 lines
3.1 KiB
YAML
109 lines
3.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=si-remove-short-exec-branches -amdgpu-skip-threshold=10 -verify-machineinstrs %s -o - | FileCheck %s
|
|
# Make sure mandatory skips are not removed around mode defs.
|
|
# FIXME: -amdgpu-skip-threshold seems to be backwards.
|
|
|
|
---
|
|
|
|
name: need_skip_gpr_idx_mode
|
|
body: |
|
|
; CHECK-LABEL: name: need_skip_gpr_idx_mode
|
|
; CHECK: bb.0:
|
|
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
|
; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
|
|
; CHECK: bb.1:
|
|
; CHECK: successors: %bb.2(0x80000000)
|
|
; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
; CHECK: S_SET_GPR_IDX_MODE 0, implicit-def $mode, implicit-def $m0, implicit $mode, implicit $m0
|
|
; CHECK: bb.2:
|
|
; CHECK: S_ENDPGM 0
|
|
bb.0:
|
|
S_CBRANCH_EXECZ %bb.2, implicit $exec
|
|
|
|
bb.1:
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
S_SET_GPR_IDX_MODE 0, implicit-def $mode, implicit-def $m0, implicit $mode, implicit $m0
|
|
|
|
bb.2:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
---
|
|
|
|
name: need_skip_gpr_idx_on
|
|
body: |
|
|
; CHECK-LABEL: name: need_skip_gpr_idx_on
|
|
; CHECK: bb.0:
|
|
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
|
; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
|
|
; CHECK: bb.1:
|
|
; CHECK: successors: %bb.2(0x80000000)
|
|
; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
; CHECK: S_SET_GPR_IDX_ON $sgpr0, 0, implicit-def $mode, implicit-def $m0, implicit $mode, implicit $m0
|
|
; CHECK: bb.2:
|
|
; CHECK: S_ENDPGM 0
|
|
bb.0:
|
|
liveins: $sgpr0
|
|
S_CBRANCH_EXECZ %bb.2, implicit $exec
|
|
|
|
bb.1:
|
|
liveins: $sgpr0
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
S_SET_GPR_IDX_ON $sgpr0, 0, implicit-def $mode, implicit-def $m0, implicit $mode, implicit $m0
|
|
|
|
bb.2:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
---
|
|
|
|
name: need_skip_gpr_idx_off
|
|
body: |
|
|
; CHECK-LABEL: name: need_skip_gpr_idx_off
|
|
; CHECK: bb.0:
|
|
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
|
; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
|
|
; CHECK: bb.1:
|
|
; CHECK: successors: %bb.2(0x80000000)
|
|
; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
; CHECK: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
|
|
; CHECK: bb.2:
|
|
; CHECK: S_ENDPGM 0
|
|
bb.0:
|
|
S_CBRANCH_EXECZ %bb.2, implicit $exec
|
|
|
|
bb.1:
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
|
|
|
|
bb.2:
|
|
S_ENDPGM 0
|
|
...
|
|
|
|
---
|
|
|
|
name: need_skip_gpr_idx_idx
|
|
body: |
|
|
; CHECK-LABEL: name: need_skip_gpr_idx_idx
|
|
; CHECK: bb.0:
|
|
; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
|
; CHECK: S_CBRANCH_EXECZ %bb.2, implicit $exec
|
|
; CHECK: bb.1:
|
|
; CHECK: successors: %bb.2(0x80000000)
|
|
; CHECK: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
; CHECK: S_SET_GPR_IDX_IDX $sgpr0, implicit-def $mode, implicit-def $m0, implicit $mode, implicit $m0
|
|
; CHECK: bb.2:
|
|
; CHECK: S_ENDPGM 0
|
|
bb.0:
|
|
liveins: $sgpr0
|
|
S_CBRANCH_EXECZ %bb.2, implicit $exec
|
|
|
|
bb.1:
|
|
liveins: $sgpr0
|
|
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
|
|
S_SET_GPR_IDX_IDX $sgpr0, implicit-def $mode, implicit-def $m0, implicit $mode, implicit $m0
|
|
|
|
bb.2:
|
|
S_ENDPGM 0
|
|
...
|