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https://github.com/RPCS3/llvm-mirror.git
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194 lines
7.0 KiB
LLVM
194 lines
7.0 KiB
LLVM
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=TOVGPR -check-prefix=GCN %s
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; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=TOVGPR -check-prefix=GCN %s
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; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=TOVMEM -check-prefix=GCN %s
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; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=TOVMEM -check-prefix=GCN %s
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; XXX - Why does it like to use vcc?
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; GCN-LABEL: {{^}}spill_m0:
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; GCN: #ASMSTART
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; GCN-NEXT: s_mov_b32 m0, 0
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; GCN-NEXT: #ASMEND
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; GCN-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0
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; TOVGPR: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], [[M0_LANE:[0-9]+]]
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; TOVMEM: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], 0
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; TOVMEM: s_mov_b32 [[COPY_EXEC_LO:s[0-9]+]], exec_lo
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; TOVMEM: s_mov_b32 exec_lo, 1
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; TOVMEM: buffer_store_dword [[SPILL_VREG]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4 ; 4-byte Folded Spill
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; TOVMEM: s_mov_b32 exec_lo, [[COPY_EXEC_LO]]
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; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]]
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; GCN: [[ENDIF]]:
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; TOVGPR: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[SPILL_VREG]], [[M0_LANE]]
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; TOVGPR: s_mov_b32 m0, [[M0_RESTORE]]
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; TOVMEM: buffer_load_dword [[RELOAD_VREG:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4 ; 4-byte Folded Reload
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; TOVMEM: s_waitcnt vmcnt(0)
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; TOVMEM: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[RELOAD_VREG]], 0
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; TOVMEM: s_mov_b32 m0, [[M0_RESTORE]]
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; GCN: s_add_i32 s{{[0-9]+}}, m0, 1
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define amdgpu_kernel void @spill_m0(i32 %cond, i32 addrspace(1)* %out) #0 {
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entry:
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%m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0
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%cmp0 = icmp eq i32 %cond, 0
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br i1 %cmp0, label %if, label %endif
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if:
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call void asm sideeffect "v_nop", ""() #0
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br label %endif
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endif:
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%foo = call i32 asm sideeffect "s_add_i32 $0, $1, 1", "=s,{m0}"(i32 %m0) #0
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store i32 %foo, i32 addrspace(1)* %out
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ret void
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}
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@lds = internal addrspace(3) global [64 x float] undef
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; m0 is killed, so it isn't necessary during the entry block spill to preserve it
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; GCN-LABEL: {{^}}spill_kill_m0_lds:
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; GCN-NOT: v_readlane_b32 m0
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; GCN-NOT: s_buffer_store_dword m0
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; GCN-NOT: s_buffer_load_dword m0
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define amdgpu_ps void @spill_kill_m0_lds(<16 x i8> addrspace(4)* inreg %arg, <16 x i8> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %m0) #0 {
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main_body:
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%tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0)
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%cmp = fcmp ueq float 0.000000e+00, %tmp
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br i1 %cmp, label %if, label %else
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if: ; preds = %main_body
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%lds_ptr = getelementptr [64 x float], [64 x float] addrspace(3)* @lds, i32 0, i32 0
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%lds_data_ = load float, float addrspace(3)* %lds_ptr
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%lds_data = call float @llvm.amdgcn.wqm.f32(float %lds_data_)
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br label %endif
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else: ; preds = %main_body
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%interp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0)
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br label %endif
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endif: ; preds = %else, %if
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%export = phi float [ %lds_data, %if ], [ %interp, %else ]
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%tmp4 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %export, float %export)
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp4, <2 x half> %tmp4, i1 true, i1 true) #0
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ret void
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}
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; Force save and restore of m0 during SMEM spill
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; GCN-LABEL: {{^}}m0_unavailable_spill:
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; GCN: s_load_dword [[REG0:s[0-9]+]], s[0:1], {{0x[0-9]+}}
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; GCN: ; def m0, 1
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; GCN: s_mov_b32 m0, [[REG0]]
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; GCN: v_interp_mov_f32
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; GCN: ; clobber m0
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; TOSMEM: s_mov_b32 s2, m0
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; TOSMEM: s_add_u32 m0, s3, 0x100
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; TOSMEM-NEXT: s_buffer_store_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 8-byte Folded Spill
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; TOSMEM: s_mov_b32 m0, s2
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; TOSMEM: s_mov_b64 exec,
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; TOSMEM: s_cbranch_execz
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; TOSMEM: s_branch
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; TOSMEM: BB{{[0-9]+_[0-9]+}}:
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; TOSMEM: s_add_u32 m0, s3, 0x100
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; TOSMEM-NEXT: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 8-byte Folded Reload
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; GCN-NOT: v_readlane_b32 m0
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; GCN-NOT: s_buffer_store_dword m0
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; GCN-NOT: s_buffer_load_dword m0
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define amdgpu_kernel void @m0_unavailable_spill(i32 %m0.arg) #0 {
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main_body:
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%m0 = call i32 asm sideeffect "; def $0, 1", "={m0}"() #0
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%tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0.arg)
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call void asm sideeffect "; clobber $0", "~{m0}"() #0
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%cmp = fcmp ueq float 0.000000e+00, %tmp
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br i1 %cmp, label %if, label %else
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if: ; preds = %main_body
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store volatile i32 8, i32 addrspace(1)* undef
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br label %endif
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else: ; preds = %main_body
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store volatile i32 11, i32 addrspace(1)* undef
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br label %endif
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endif:
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ret void
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}
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; GCN-LABEL: {{^}}restore_m0_lds:
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; FIXME: RegScavenger::isRegUsed() always returns true if m0 is reserved, so we have to save and restore it
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; FIXME-TOSMEM-NOT: m0
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; TOSMEM: s_add_u32 m0, s3, {{0x[0-9]+}}
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; TOSMEM: s_buffer_store_dword s1, s[88:91], m0 ; 4-byte Folded Spill
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; FIXME-TOSMEM-NOT: m0
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; TOSMEM: s_load_dwordx2 [[REG:s\[[0-9]+:[0-9]+\]]]
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; TOSMEM: s_add_u32 m0, s3, {{0x[0-9]+}}
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; TOSMEM: s_waitcnt lgkmcnt(0)
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; TOSMEM: s_buffer_store_dwordx2 [[REG]], s[88:91], m0 ; 8-byte Folded Spill
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; FIXME-TOSMEM-NOT: m0
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; TOSMEM: s_cmp_eq_u32
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; TOSMEM: s_cbranch_scc1
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; TOSMEM: s_mov_b32 m0, -1
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; TOSMEM: s_mov_b32 s2, m0
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; TOSMEM: s_add_u32 m0, s3, 0x200
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; TOSMEM: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[88:91], m0 ; 8-byte Folded Reload
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; TOSMEM: s_mov_b32 m0, s2
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; TOSMEM: s_waitcnt lgkmcnt(0)
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; TOSMEM: ds_write_b64
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; FIXME-TOSMEM-NOT: m0
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; TOSMEM: s_add_u32 m0, s3, 0x100
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; TOSMEM: s_buffer_load_dword s2, s[88:91], m0 ; 4-byte Folded Reload
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; FIXME-TOSMEM-NOT: m0
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; TOSMEM: s_mov_b32 [[REG1:s[0-9]+]], m0
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; TOSMEM: s_add_u32 m0, s3, 0x100
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; TOSMEM: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[88:91], m0 ; 8-byte Folded Reload
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; TOSMEM: s_mov_b32 m0, [[REG1]]
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; TOSMEM: s_mov_b32 m0, -1
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; TOSMEM: s_waitcnt lgkmcnt(0)
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; TOSMEM-NOT: m0
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; TOSMEM: s_mov_b32 m0, s2
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; TOSMEM: ; use m0
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; TOSMEM: s_dcache_wb
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; TOSMEM: s_endpgm
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define amdgpu_kernel void @restore_m0_lds(i32 %arg) {
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%m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0
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%sval = load volatile i64, i64 addrspace(4)* undef
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%cmp = icmp eq i32 %arg, 0
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br i1 %cmp, label %ret, label %bb
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bb:
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store volatile i64 %sval, i64 addrspace(3)* undef
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call void asm sideeffect "; use $0", "{m0}"(i32 %m0) #0
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br label %ret
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ret:
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ret void
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}
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declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
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declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0
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declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
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declare float @llvm.amdgcn.wqm.f32(float) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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