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ab043ff680
Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
64 lines
1.5 KiB
LLVM
64 lines
1.5 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
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;; i8
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define i8 @ld_global_i8(i8 addrspace(0)* %ptr) {
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; PTX32: ld.u8 %r{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load i8, i8 addrspace(0)* %ptr
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ret i8 %a
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}
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;; i16
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define i16 @ld_global_i16(i16 addrspace(0)* %ptr) {
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; PTX32: ld.u16 %r{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load i16, i16 addrspace(0)* %ptr
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ret i16 %a
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}
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;; i32
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define i32 @ld_global_i32(i32 addrspace(0)* %ptr) {
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; PTX32: ld.u32 %r{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load i32, i32 addrspace(0)* %ptr
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ret i32 %a
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}
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;; i64
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define i64 @ld_global_i64(i64 addrspace(0)* %ptr) {
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; PTX32: ld.u64 %rd{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load i64, i64 addrspace(0)* %ptr
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ret i64 %a
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}
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;; f32
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define float @ld_global_f32(float addrspace(0)* %ptr) {
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; PTX32: ld.f32 %f{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.f32 %f{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load float, float addrspace(0)* %ptr
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ret float %a
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}
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;; f64
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define double @ld_global_f64(double addrspace(0)* %ptr) {
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; PTX32: ld.f64 %fd{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.f64 %fd{{[0-9]+}}, [%rd{{[0-9]+}}]
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; PTX64: ret
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%a = load double, double addrspace(0)* %ptr
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ret double %a
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}
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