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330 lines
12 KiB
C++
330 lines
12 KiB
C++
//===- AMDGPURegisterBankInfo.cpp -------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the RegisterBankInfo class for
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/// AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "AMDGPURegisterBankInfo.h"
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#include "AMDGPUInstrInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/Constants.h"
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#define GET_TARGET_REGBANK_IMPL
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#include "AMDGPUGenRegisterBank.inc"
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// This file will be TableGen'ed at some point.
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#include "AMDGPUGenRegisterBankInfo.def"
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using namespace llvm;
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AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI)
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: AMDGPUGenRegisterBankInfo(),
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TRI(static_cast<const SIRegisterInfo*>(&TRI)) {
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// HACK: Until this is fully tablegen'd
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static bool AlreadyInit = false;
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if (AlreadyInit)
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return;
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AlreadyInit = true;
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const RegisterBank &RBSGPR = getRegBank(AMDGPU::SGPRRegBankID);
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(void)RBSGPR;
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assert(&RBSGPR == &AMDGPU::SGPRRegBank);
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const RegisterBank &RBVGPR = getRegBank(AMDGPU::VGPRRegBankID);
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(void)RBVGPR;
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assert(&RBVGPR == &AMDGPU::VGPRRegBank);
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}
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unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
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const RegisterBank &Src,
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unsigned Size) const {
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if (Dst.getID() == AMDGPU::SGPRRegBankID &&
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Src.getID() == AMDGPU::VGPRRegBankID)
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return std::numeric_limits<unsigned>::max();
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// SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by
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// the valu.
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if (Size == 1 && Dst.getID() == AMDGPU::SCCRegBankID &&
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Src.getID() == AMDGPU::SGPRRegBankID)
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return std::numeric_limits<unsigned>::max();
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return RegisterBankInfo::copyCost(Dst, Src, Size);
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}
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const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass(
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const TargetRegisterClass &RC) const {
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if (TRI->isSGPRClass(&RC))
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return getRegBank(AMDGPU::SGPRRegBankID);
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return getRegBank(AMDGPU::VGPRRegBankID);
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}
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RegisterBankInfo::InstructionMappings
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AMDGPURegisterBankInfo::getInstrAlternativeMappings(
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const MachineInstr &MI) const {
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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InstructionMappings AltMappings;
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switch (MI.getOpcode()) {
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case TargetOpcode::G_LOAD: {
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unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
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// FIXME: Should we be hard coding the size for these mappings?
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const InstructionMapping &SSMapping = getInstructionMapping(
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1, 1, getOperandsMapping(
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{AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 64)}),
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2); // Num Operands
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AltMappings.push_back(&SSMapping);
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const InstructionMapping &VVMapping = getInstructionMapping(
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2, 1, getOperandsMapping(
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{AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64)}),
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2); // Num Operands
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AltMappings.push_back(&VVMapping);
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// FIXME: Should this be the pointer-size (64-bits) or the size of the
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// register that will hold the bufffer resourc (128-bits).
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const InstructionMapping &VSMapping = getInstructionMapping(
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3, 1, getOperandsMapping(
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{AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 64)}),
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2); // Num Operands
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AltMappings.push_back(&VSMapping);
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return AltMappings;
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}
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case TargetOpcode::G_ICMP: {
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unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
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const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, 1),
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nullptr, // Predicate operand.
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&SSMapping);
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const InstructionMapping &SVMapping = getInstructionMapping(2, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
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nullptr, // Predicate operand.
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&SVMapping);
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const InstructionMapping &VSMapping = getInstructionMapping(3, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
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nullptr, // Predicate operand.
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&VSMapping);
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const InstructionMapping &VVMapping = getInstructionMapping(4, 1,
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getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
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nullptr, // Predicate operand.
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
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4); // Num Operands
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AltMappings.push_back(&VVMapping);
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return AltMappings;
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}
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default:
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break;
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}
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return RegisterBankInfo::getInstrAlternativeMappings(MI);
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}
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void AMDGPURegisterBankInfo::applyMappingImpl(
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const OperandsMapper &OpdMapper) const {
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return applyDefaultMapping(OpdMapper);
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}
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static bool isInstrUniform(const MachineInstr &MI) {
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if (!MI.hasOneMemOperand())
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return false;
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const MachineMemOperand *MMO = *MI.memoperands_begin();
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return AMDGPUInstrInfo::isUniformMMO(MMO);
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}
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const RegisterBankInfo::InstructionMapping &
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AMDGPURegisterBankInfo::getInstrMappingForLoad(const MachineInstr &MI) const {
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
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unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
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unsigned PtrSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
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const ValueMapping *ValMapping;
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const ValueMapping *PtrMapping;
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if (isInstrUniform(MI)) {
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// We have a uniform instruction so we want to use an SMRD load
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ValMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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PtrMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize);
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} else {
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ValMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
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// FIXME: What would happen if we used SGPRRegBankID here?
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PtrMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, PtrSize);
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}
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OpdsMapping[0] = ValMapping;
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OpdsMapping[1] = PtrMapping;
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const RegisterBankInfo::InstructionMapping &Mapping = getInstructionMapping(
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1, 1, getOperandsMapping(OpdsMapping), MI.getNumOperands());
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return Mapping;
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// FIXME: Do we want to add a mapping for FLAT load, or should we just
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// handle that during instruction selection?
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}
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unsigned
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AMDGPURegisterBankInfo::getRegBankID(unsigned Reg,
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const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI,
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unsigned Default) const {
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const RegisterBank *Bank = getRegBank(Reg, MRI, TRI);
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return Bank ? Bank->getID() : Default;
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}
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///
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/// This function must return a legal mapping, because
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/// AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called
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/// in RegBankSelect::Mode::Fast. Any mapping that would cause a
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/// VGPR to SGPR generated is illegal.
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///
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const RegisterBankInfo::InstructionMapping &
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AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
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if (Mapping.isValid())
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return Mapping;
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
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bool IsComplete = true;
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switch (MI.getOpcode()) {
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default:
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IsComplete = false;
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break;
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case AMDGPU::G_IMPLICIT_DEF: {
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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break;
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}
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case AMDGPU::G_FCONSTANT:
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case AMDGPU::G_CONSTANT: {
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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break;
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}
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case AMDGPU::G_GEP: {
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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if (!MI.getOperand(i).isReg())
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continue;
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unsigned Size = MRI.getType(MI.getOperand(i).getReg()).getSizeInBits();
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OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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}
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break;
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}
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case AMDGPU::G_STORE: {
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assert(MI.getOperand(0).isReg());
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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// FIXME: We need to specify a different reg bank once scalar stores
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// are supported.
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const ValueMapping *ValMapping =
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
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// FIXME: Depending on the type of store, the pointer could be in
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// the SGPR Reg bank.
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// FIXME: Pointer size should be based on the address space.
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const ValueMapping *PtrMapping =
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AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64);
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OpdsMapping[0] = ValMapping;
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OpdsMapping[1] = PtrMapping;
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break;
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}
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case AMDGPU::G_ICMP: {
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unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
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unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
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unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
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unsigned Op0Bank = Op2Bank == AMDGPU::SGPRRegBankID &&
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Op3Bank == AMDGPU::SGPRRegBankID ?
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AMDGPU::SCCRegBankID : AMDGPU::VGPRRegBankID;
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OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, 1);
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OpdsMapping[1] = nullptr; // Predicate Operand.
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OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
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OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
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break;
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}
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case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: {
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unsigned IntrinsicID = MI.getOperand(0).getIntrinsicID();
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switch (IntrinsicID) {
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case Intrinsic::amdgcn_exp: {
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OpdsMapping[0] = nullptr; // IntrinsicID
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// FIXME: These are immediate values which can't be read from registers.
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OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
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OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
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// FIXME: Could we support packed types here?
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OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
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OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
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OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
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OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
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// FIXME: These are immediate values which can't be read from registers.
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OpdsMapping[7] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
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OpdsMapping[8] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32);
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break;
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}
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}
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break;
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}
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case AMDGPU::G_LOAD:
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return getInstrMappingForLoad(MI);
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}
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if (!IsComplete) {
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unsigned BankID = AMDGPU::SGPRRegBankID;
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unsigned Size = 0;
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for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx) {
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// If the operand is not a register default to the size of the previous
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// operand.
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// FIXME: Can't we pull the types from the MachineInstr rather than the
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// operands.
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if (MI.getOperand(Idx).isReg())
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Size = getSizeInBits(MI.getOperand(Idx).getReg(), MRI, *TRI);
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OpdsMapping.push_back(AMDGPU::getValueMapping(BankID, Size));
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}
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}
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return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
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MI.getNumOperands());
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}
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