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5efe040582
Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
96 lines
2.8 KiB
LLVM
96 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-ios -asm-verbose=false \
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; RUN: -aarch64-enable-collect-loh=false -aarch64-enable-global-merge \
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; RUN: -global-merge-group-by-use -global-merge-ignore-single-use=false %s \
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; RUN: -o - | FileCheck %s
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; We assume that globals of the same size aren't reordered inside a set.
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; Check that we create two MergedGlobal instances for two functions using
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; disjoint sets of globals
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@m1 = internal global i32 0, align 4
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@n1 = internal global i32 0, align 4
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; CHECK-LABEL: f1:
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define void @f1(i32 %a1, i32 %a2) #0 {
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; CHECK-NEXT: adrp x8, [[SET1:l__MergedGlobals.[0-9]*]]@PAGE
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; CHECK-NEXT: add x8, x8, [[SET1]]@PAGEOFF
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; CHECK-NEXT: stp w0, w1, [x8]
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; CHECK-NEXT: ret
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store i32 %a1, i32* @m1, align 4
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store i32 %a2, i32* @n1, align 4
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ret void
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}
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@m2 = internal global i32 0, align 4
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@n2 = internal global i32 0, align 4
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@o2 = internal global i32 0, align 4
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; CHECK-LABEL: f2:
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define void @f2(i32 %a1, i32 %a2, i32 %a3) #0 {
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; CHECK-NEXT: adrp x8, [[SET2:l__MergedGlobals.[0-9]*]]@PAGE
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; CHECK-NEXT: add x8, x8, [[SET2]]@PAGEOFF
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; CHECK-NEXT: stp w0, w1, [x8]
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; CHECK-NEXT: str w2, [x8, #8]
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; CHECK-NEXT: ret
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store i32 %a1, i32* @m2, align 4
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store i32 %a2, i32* @n2, align 4
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store i32 %a3, i32* @o2, align 4
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ret void
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}
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; Sanity-check (don't worry about cost models) that we pick the biggest subset
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; of all global used "together" directly or indirectly. Here, that means
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; merging n3, m4, and n4 together, but ignoring m3.
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@m3 = internal global i32 0, align 4
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@n3 = internal global i32 0, align 4
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; CHECK-LABEL: f3:
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define void @f3(i32 %a1, i32 %a2) #0 {
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; CHECK-NEXT: adrp x8, _m3@PAGE
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; CHECK-NEXT: adrp x9, [[SET3:l__MergedGlobals[0-9]*]]@PAGE
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; CHECK-NEXT: str w0, [x8, _m3@PAGEOFF]
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; CHECK-NEXT: str w1, [x9, [[SET3]]@PAGEOFF]
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; CHECK-NEXT: ret
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store i32 %a1, i32* @m3, align 4
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store i32 %a2, i32* @n3, align 4
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ret void
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}
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@m4 = internal global i32 0, align 4
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@n4 = internal global i32 0, align 4
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; CHECK-LABEL: f4:
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define void @f4(i32 %a1, i32 %a2, i32 %a3) #0 {
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; CHECK-NEXT: adrp x8, [[SET3]]@PAGE
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; CHECK-NEXT: add x8, x8, [[SET3]]@PAGEOFF
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; CHECK-NEXT: stp w2, w0, [x8]
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; CHECK-NEXT: str w1, [x8, #8]
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; CHECK-NEXT: ret
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store i32 %a1, i32* @m4, align 4
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store i32 %a2, i32* @n4, align 4
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store i32 %a3, i32* @n3, align 4
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ret void
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}
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; Finally, check that we don't do anything with one-element global sets.
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@o5 = internal global i32 0, align 4
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; CHECK-LABEL: f5:
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define void @f5(i32 %a1) #0 {
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; CHECK-NEXT: adrp x8, _o5@PAGE
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; CHECK-NEXT: str w0, [x8, _o5@PAGEOFF]
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; CHECK-NEXT: ret
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store i32 %a1, i32* @o5, align 4
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ret void
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}
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; CHECK-DAG: .zerofill __DATA,__bss,_o5,4,2
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; CHECK-DAG: .zerofill __DATA,__bss,[[SET1]],8,3
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; CHECK-DAG: .zerofill __DATA,__bss,[[SET2]],12,3
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; CHECK-DAG: .zerofill __DATA,__bss,[[SET3]],12,3
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attributes #0 = { nounwind }
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