mirror of
https://github.com/RPCS3/llvm-mirror.git
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1c614b247d
llvm-svn: 188454
67 lines
2.0 KiB
LLVM
67 lines
2.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; CHECK: LCP
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; CHECK: .long 2
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; CHECK: .long 5
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; CHECK: .long 0
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; CHECK: .long 0
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; CHECK: .long 7
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; CHECK: .long 0
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; CHECK: .long 10
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; CHECK: .long 1
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; CHECK: .long 0
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; CHECK: .long 5
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; CHECK: .long 0
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; CHECK: .long 4
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; CHECK: .long 7
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; CHECK: .long 0
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; CHECK: .long 10
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; CHECK: .long 1
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; CHECK: test1:
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; CHECK: vpermps
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; CHECK: ret
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define <16 x float> @test1(<16 x float> %a) nounwind {
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%c = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1>
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ret <16 x float> %c
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}
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; CHECK: test2:
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; CHECK: vpermd
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; CHECK: ret
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define <16 x i32> @test2(<16 x i32> %a) nounwind {
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%c = shufflevector <16 x i32> %a, <16 x i32> undef, <16 x i32> <i32 2, i32 5, i32 undef, i32 undef, i32 7, i32 undef, i32 10, i32 1, i32 0, i32 5, i32 undef, i32 4, i32 7, i32 undef, i32 10, i32 1>
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ret <16 x i32> %c
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}
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; CHECK: test3:
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; CHECK: vpermq
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; CHECK: ret
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define <8 x i64> @test3(<8 x i64> %a) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 5, i32 1, i32 undef, i32 7, i32 undef, i32 3, i32 1>
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ret <8 x i64> %c
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}
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; CHECK: test4:
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; CHECK: vpermpd
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; CHECK: ret
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define <8 x double> @test4(<8 x double> %a) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> undef, <8 x i32> <i32 1, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <8 x double> %c
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}
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; CHECK: test5:
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; CHECK: vpermi2pd
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; CHECK: ret
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define <8 x double> @test5(<8 x double> %a, <8 x double> %b) nounwind {
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%c = shufflevector <8 x double> %a, <8 x double> %b, <8 x i32> <i32 2, i32 8, i32 0, i32 1, i32 6, i32 10, i32 4, i32 5>
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ret <8 x double> %c
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}
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; CHECK: test6:
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; CHECK: vpermq $30
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; CHECK: ret
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define <8 x i64> @test6(<8 x i64> %a) nounwind {
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%c = shufflevector <8 x i64> %a, <8 x i64> undef, <8 x i32> <i32 2, i32 3, i32 1, i32 0, i32 6, i32 7, i32 5, i32 4>
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ret <8 x i64> %c
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}
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