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8b3f28cdb1
Summary: [X86][GlobalISel] Add general-purpose Register Bank. Add trivial handling of G_ADD legalization . Add Regestry Bank selection for COPY and G_ADD instructions Reviewers: rovka, zvi, ab, t.p.northover, qcolombet Reviewed By: qcolombet Subscribers: qcolombet, mgorny, dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29771 llvm-svn: 294723
61 lines
1.8 KiB
C++
61 lines
1.8 KiB
C++
//===- X86GenRegisterBankInfo.def ----------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines all the static objects used by X86RegisterBankInfo.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "You shouldn't build this"
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#endif
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namespace llvm {
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RegisterBankInfo::PartialMapping X86GenRegisterBankInfo::PartMappings[]{
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/* StartIdx, Length, RegBank */
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// GPR value
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{0, 8, X86::GPRRegBank}, // :0
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{0, 16, X86::GPRRegBank}, // :1
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{0, 32, X86::GPRRegBank}, // :2
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{0, 64, X86::GPRRegBank}, // :3
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};
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enum PartialMappingIdx {
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PMI_None = -1,
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PMI_GPR8,
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PMI_GPR16,
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PMI_GPR32,
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PMI_GPR64,
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};
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#define INSTR_3OP(INFO) INFO, INFO, INFO,
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#define BREAKDOWN(INDEX, NUM) \
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{ &X86GenRegisterBankInfo::PartMappings[INDEX], NUM }
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// ValueMappings.
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RegisterBankInfo::ValueMapping X86GenRegisterBankInfo::ValMappings[]{
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/* BreakDown, NumBreakDowns */
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// 3-operands instructions (all binary operations should end up with one of
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// those mapping).
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INSTR_3OP(BREAKDOWN(PMI_GPR8, 1)) // 0: GPR_8
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INSTR_3OP(BREAKDOWN(PMI_GPR16, 1)) // 3: GPR_16
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INSTR_3OP(BREAKDOWN(PMI_GPR32, 1)) // 6: GPR_32
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INSTR_3OP(BREAKDOWN(PMI_GPR64, 1)) // 9: GPR_64
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};
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#undef INSTR_3OP
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#undef BREAKDOWN
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enum ValueMappingIdx {
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VMI_None = -1,
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VMI_3OpsGpr8Idx = 0,
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VMI_3OpsGpr16Idx = 3,
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VMI_3OpsGpr32Idx = 6,
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VMI_3OpsGpr64Idx = 9,
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};
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} // End llvm namespace.
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