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llvm-mirror/test/CodeGen/Hexagon/build-vector-shuffle.ll
Sumanth Gundapaneni 262321d1ff [Hexagon] New HVX target features.
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"

For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"

Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.

Differential Revision: https://reviews.llvm.org/D38851

llvm-svn: 316101
2017-10-18 18:07:07 +00:00

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706 B
LLVM

; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that we don't crash.
; CHECK: vshuff
target triple = "hexagon"
define void @hex_interleaved.s0.__outermost() local_unnamed_addr #0 {
entry:
%0 = icmp eq i32 undef, 0
%sel2 = select i1 %0, <32 x i16> undef, <32 x i16> zeroinitializer
%1 = bitcast <32 x i16> %sel2 to <16 x i32>
%2 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %1)
store <16 x i32> %2, <16 x i32>* undef, align 2
unreachable
}
; Function Attrs: nounwind readnone
declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }