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92ce5b3319
Summary: Currently, we only have nice exploration for LEA instruction, while for the rest, we rely on `randomizeUnsetVariables()` to sometimes generate something interesting. While that works, it isn't very reliable in coverage :) Here, i'm making an assumption that while we may want to explore multi-instruction configs, we are most interested in the characteristics of the main instruction we were asked about. Which we can do, by taking the existing `randomizeMCOperand()`, and turning it on it's head - instead of relying on it to randomly fill one of the interesting values, let's pregenerate all the possible interesting values for the variable, and then generate as much `InstructionTemplate` combinations of these possible values for variables as needed/possible. Of course, that requires invasive changes to no longer pass just the naked `Instruction`, but sometimes partially filled `InstructionTemplate`. As it can be seen from the test, this allows us to explore `X86::OperandType::OPERAND_COND_CODE` for instructions that take such an operand. I'm hoping this will greatly simplify exploration. Reviewers: courbet, gchatelet Reviewed By: gchatelet Subscribers: orodley, mgorny, sdardis, tschuett, jrtc27, atanasyan, mstojanovic, andreadb, RKSimon, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74156
185 lines
7.2 KiB
C++
185 lines
7.2 KiB
C++
//===-- Target.h ------------------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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///
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/// Classes that handle the creation of target-specific objects. This is
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/// similar to Target/TargetRegistry.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_EXEGESIS_TARGET_H
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#define LLVM_TOOLS_LLVM_EXEGESIS_TARGET_H
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#include "BenchmarkResult.h"
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#include "BenchmarkRunner.h"
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#include "Error.h"
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#include "LlvmState.h"
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#include "SnippetGenerator.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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namespace llvm {
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namespace exegesis {
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struct PfmCountersInfo {
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// An optional name of a performance counter that can be used to measure
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// cycles.
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const char *CycleCounter;
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// An optional name of a performance counter that can be used to measure
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// uops.
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const char *UopsCounter;
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// An IssueCounter specifies how to measure uops issued to specific proc
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// resources.
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struct IssueCounter {
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const char *Counter;
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// The name of the ProcResource that this counter measures.
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const char *ProcResName;
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};
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// An optional list of IssueCounters.
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const IssueCounter *IssueCounters;
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unsigned NumIssueCounters;
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static const PfmCountersInfo Default;
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};
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struct CpuAndPfmCounters {
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const char *CpuName;
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const PfmCountersInfo *PCI;
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bool operator<(StringRef S) const { return StringRef(CpuName) < S; }
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};
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class ExegesisTarget {
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public:
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explicit ExegesisTarget(ArrayRef<CpuAndPfmCounters> CpuPfmCounters)
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: CpuPfmCounters(CpuPfmCounters) {}
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// Targets can use this to add target-specific passes in assembleToStream();
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virtual void addTargetSpecificPasses(PassManagerBase &PM) const {}
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// Generates code to move a constant into a the given register.
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// Precondition: Value must fit into Reg.
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virtual std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
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const APInt &Value) const = 0;
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// Returns the register pointing to scratch memory, or 0 if this target
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// does not support memory operands. The benchmark function uses the
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// default calling convention.
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virtual unsigned getScratchMemoryRegister(const Triple &) const { return 0; }
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// Fills memory operands with references to the address at [Reg] + Offset.
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virtual void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
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unsigned Offset) const {
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llvm_unreachable(
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"fillMemoryOperands() requires getScratchMemoryRegister() > 0");
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}
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// Returns a counter usable as a loop counter.
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virtual unsigned getLoopCounterRegister(const Triple &) const { return 0; }
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// Adds the code to decrement the loop counter and
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virtual void decrementLoopCounterAndJump(MachineBasicBlock &MBB,
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MachineBasicBlock &TargetMBB,
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const MCInstrInfo &MII) const {
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llvm_unreachable("decrementLoopCounterAndBranch() requires "
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"getLoopCounterRegister() > 0");
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}
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// Returns a list of unavailable registers.
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// Targets can use this to prevent some registers to be automatically selected
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// for use in snippets.
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virtual ArrayRef<unsigned> getUnavailableRegisters() const { return {}; }
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// Returns the maximum number of bytes a load/store instruction can access at
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// once. This is typically the size of the largest register available on the
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// processor. Note that this only used as a hint to generate independant
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// load/stores to/from memory, so the exact returned value does not really
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// matter as long as it's large enough.
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virtual unsigned getMaxMemoryAccessSize() const { return 0; }
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// Assigns a random operand of the right type to variable Var.
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// The target is responsible for handling any operand starting from
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// OPERAND_FIRST_TARGET.
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virtual Error randomizeTargetMCOperand(const Instruction &Instr,
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const Variable &Var,
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MCOperand &AssignedValue,
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const BitVector &ForbiddenRegs) const {
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return make_error<Failure>(
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"targets with target-specific operands should implement this");
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}
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// Returns true if this instruction is supported as a back-to-back
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// instructions.
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// FIXME: Eventually we should discover this dynamically.
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virtual bool allowAsBackToBack(const Instruction &Instr) const {
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return true;
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}
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// For some instructions, it is interesting to measure how it's performance
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// characteristics differ depending on it's operands.
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// This allows us to produce all the interesting variants.
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virtual std::vector<InstructionTemplate>
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generateInstructionVariants(const Instruction &Instr,
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unsigned MaxConfigsPerOpcode) const {
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// By default, we're happy with whatever randomizer will give us.
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return {&Instr};
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}
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// Creates a snippet generator for the given mode.
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std::unique_ptr<SnippetGenerator>
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createSnippetGenerator(InstructionBenchmark::ModeE Mode,
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const LLVMState &State,
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const SnippetGenerator::Options &Opts) const;
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// Creates a benchmark runner for the given mode.
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Expected<std::unique_ptr<BenchmarkRunner>>
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createBenchmarkRunner(InstructionBenchmark::ModeE Mode,
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const LLVMState &State) const;
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// Returns the ExegesisTarget for the given triple or nullptr if the target
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// does not exist.
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static const ExegesisTarget *lookup(Triple TT);
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// Returns the default (unspecialized) ExegesisTarget.
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static const ExegesisTarget &getDefault();
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// Registers a target. Not thread safe.
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static void registerTarget(ExegesisTarget *T);
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virtual ~ExegesisTarget();
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// Returns the Pfm counters for the given CPU (or the default if no pfm
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// counters are defined for this CPU).
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const PfmCountersInfo &getPfmCounters(StringRef CpuName) const;
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private:
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virtual bool matchesArch(Triple::ArchType Arch) const = 0;
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// Targets can implement their own snippet generators/benchmarks runners by
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// implementing these.
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std::unique_ptr<SnippetGenerator> virtual createSerialSnippetGenerator(
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const LLVMState &State, const SnippetGenerator::Options &Opts) const;
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std::unique_ptr<SnippetGenerator> virtual createParallelSnippetGenerator(
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const LLVMState &State, const SnippetGenerator::Options &Opts) const;
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std::unique_ptr<BenchmarkRunner> virtual createLatencyBenchmarkRunner(
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const LLVMState &State, InstructionBenchmark::ModeE Mode) const;
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std::unique_ptr<BenchmarkRunner> virtual createUopsBenchmarkRunner(
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const LLVMState &State) const;
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const ExegesisTarget *Next = nullptr;
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const ArrayRef<CpuAndPfmCounters> CpuPfmCounters;
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};
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} // namespace exegesis
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} // namespace llvm
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#endif // LLVM_TOOLS_LLVM_EXEGESIS_TARGET_H
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