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https://github.com/RPCS3/llvm-mirror.git
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b56f57ef00
This was finding the wrong size registers for anything with more than 2 components. Patch by Tom Stellard llvm-svn: 326483
107 lines
2.5 KiB
C++
107 lines
2.5 KiB
C++
//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines all the static objects used by AMDGPURegisterBankInfo.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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namespace llvm {
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namespace AMDGPU {
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enum PartialMappingIdx {
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None = - 1,
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PM_SGPR1 = 0,
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PM_SGPR16 = 4,
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PM_SGPR32 = 5,
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PM_SGPR64 = 6,
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PM_SGPR128 = 7,
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PM_SGPR256 = 8,
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PM_SGPR512 = 9,
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PM_VGPR1 = 10,
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PM_VGPR16 = 14,
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PM_VGPR32 = 15,
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PM_VGPR64 = 16,
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PM_VGPR128 = 17,
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PM_VGPR256 = 18,
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PM_VGPR512 = 19,
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PM_SGPR96 = 20,
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PM_VGPR96 = 21
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};
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const RegisterBankInfo::PartialMapping PartMappings[] {
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// StartIdx, Length, RegBank
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{0, 1, SCCRegBank},
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{0, 16, SGPRRegBank},
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{0, 32, SGPRRegBank},
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{0, 64, SGPRRegBank},
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{0, 128, SGPRRegBank},
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{0, 256, SGPRRegBank},
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{0, 512, SGPRRegBank},
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{0, 1, SGPRRegBank},
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{0, 16, VGPRRegBank},
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{0, 32, VGPRRegBank},
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{0, 64, VGPRRegBank},
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{0, 128, VGPRRegBank},
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{0, 256, VGPRRegBank},
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{0, 512, VGPRRegBank},
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{0, 96, SGPRRegBank},
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{0, 96, VGPRRegBank},
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};
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const RegisterBankInfo::ValueMapping ValMappings[] {
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{&PartMappings[0], 1},
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{nullptr, 0},
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{nullptr, 0},
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{nullptr, 0},
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{&PartMappings[1], 1},
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{&PartMappings[2], 1},
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{&PartMappings[3], 1},
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{&PartMappings[4], 1},
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{&PartMappings[5], 1},
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{&PartMappings[6], 1},
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{&PartMappings[7], 1},
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{nullptr, 0},
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{nullptr, 0},
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{nullptr, 0},
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{&PartMappings[8], 1},
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{&PartMappings[9], 1},
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{&PartMappings[10], 1},
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{&PartMappings[11], 1},
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{&PartMappings[12], 1},
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{&PartMappings[13], 1},
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{&PartMappings[14], 1},
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{&PartMappings[15], 1}
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};
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enum ValueMappingIdx {
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SGPRStartIdx = 0,
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VGPRStartIdx = 10
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};
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const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
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unsigned Size) {
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unsigned Idx;
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switch (Size) {
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case 1:
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Idx = BankID == AMDGPU::SCCRegBankID ? PM_SGPR1 : PM_VGPR1;
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break;
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case 96:
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Idx = BankID == AMDGPU::SGPRRegBankID ? PM_SGPR96 : PM_VGPR96;
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break;
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default:
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Idx = BankID == AMDGPU::VGPRRegBankID ? VGPRStartIdx : SGPRStartIdx;
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Idx += llvm::countTrailingZeros(Size);
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break;
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}
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return &ValMappings[Idx];
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}
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} // End AMDGPU namespace.
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} // End llvm namespace.
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