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9e2adaa646
Summary: Added support for scratch (including spilling) for OS type amdpal: generates code to set up the scratch descriptor if it is needed. With amdpal, the scratch resource descriptor is loaded from offset 0 of the global information table. The low 32 bits of the address of the global information table is passed in s0. Added amdgpu-git-ptr-high function attribute to hard-wire the high 32 bits of the address of the global information table. If the function attribute is not specified, or is 0xffffffff, then the backend generates code to use the high 32 bits of pc. The documentation for the AMDPAL ABI will be added in a later commit. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye Differential Revision: https://reviews.llvm.org/D37483 llvm-svn: 314501
86 lines
2.9 KiB
C++
86 lines
2.9 KiB
C++
//===--------------------- SIFrameLowering.h --------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
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#include "AMDGPUFrameLowering.h"
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namespace llvm {
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class SIInstrInfo;
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class SIMachineFunctionInfo;
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class SIRegisterInfo;
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class SISubtarget;
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class SIFrameLowering final : public AMDGPUFrameLowering {
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public:
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SIFrameLowering(StackDirection D, unsigned StackAl, int LAO,
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unsigned TransAl = 1) :
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AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
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~SIFrameLowering() override = default;
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void emitEntryFunctionPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const;
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void emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const override;
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int getFrameIndexReference(const MachineFunction &MF, int FI,
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unsigned &FrameReg) const override;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS = nullptr) const override;
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void processFunctionBeforeFrameFinalized(
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MachineFunction &MF,
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RegScavenger *RS = nullptr) const override;
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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private:
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void emitFlatScratchInit(const SISubtarget &ST,
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MachineFunction &MF,
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MachineBasicBlock &MBB) const;
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unsigned getReservedPrivateSegmentBufferReg(
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const SISubtarget &ST,
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const SIInstrInfo *TII,
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const SIRegisterInfo *TRI,
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SIMachineFunctionInfo *MFI,
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MachineFunction &MF) const;
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std::pair<unsigned, unsigned> getReservedPrivateSegmentWaveByteOffsetReg(
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const SISubtarget &ST,
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const SIInstrInfo *TII,
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const SIRegisterInfo *TRI,
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SIMachineFunctionInfo *MFI,
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MachineFunction &MF) const;
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/// \brief Emits debugger prologue.
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void emitDebuggerPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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// Emit scratch setup code for AMDPAL or Mesa, assuming ResourceRegUsed is set.
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void emitEntryFunctionScratchSetup(const SISubtarget &ST, MachineFunction &MF,
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MachineBasicBlock &MBB, SIMachineFunctionInfo *MFI,
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MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg,
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unsigned ScratchRsrcReg) const;
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public:
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bool hasFP(const MachineFunction &MF) const override;
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bool hasSP(const MachineFunction &MF) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
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