mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
0fa09433f0
Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a🅱️c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
77 lines
3.3 KiB
LLVM
77 lines
3.3 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s
|
|
|
|
|
|
; CHECK: test1
|
|
; CHECK: movi d[[REG0:[0-9]+]], #0000000000000000
|
|
define <8 x i1> @test1() {
|
|
entry:
|
|
%Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
|
|
i1 7>,
|
|
<8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
|
|
i1 7>,
|
|
<8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10,
|
|
i32 12, i32 14, i32 0>
|
|
ret <8 x i1> %Shuff
|
|
}
|
|
|
|
; CHECK: lCPI1_0:
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 1 ; 0x1
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: test2
|
|
; CHECK: adrp x[[REG2:[0-9]+]], lCPI1_0@PAGE
|
|
; CHECK: ldr d[[REG1:[0-9]+]], [x[[REG2]], lCPI1_0@PAGEOFF]
|
|
define <8 x i1>@test2() {
|
|
bb:
|
|
%Shuff = shufflevector <8 x i1> zeroinitializer,
|
|
<8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
|
|
<8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
|
|
i32 0>
|
|
ret <8 x i1> %Shuff
|
|
}
|
|
|
|
; CHECK: test3
|
|
; CHECK: movi.4s v{{[0-9]+}}, #1
|
|
define <16 x i1> @test3(i1* %ptr, i32 %v) {
|
|
bb:
|
|
%Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <16 x i1> undef,
|
|
<16 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
|
|
i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12,
|
|
i32 14, i32 0>
|
|
ret <16 x i1> %Shuff
|
|
}
|
|
; CHECK: lCPI3_0:
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 1 ; 0x1
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: .byte 0 ; 0x0
|
|
; CHECK: _test4:
|
|
; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_0@PAGE
|
|
; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0@PAGEOFF]
|
|
define <16 x i1> @test4(i1* %ptr, i32 %v) {
|
|
bb:
|
|
%Shuff = shufflevector <16 x i1> zeroinitializer,
|
|
<16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1,
|
|
i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
|
|
<16 x i32> <i32 2, i32 1, i32 6, i32 18, i32 10, i32 12, i32 14, i32 0,
|
|
i32 2, i32 31, i32 6, i32 30, i32 10, i32 12, i32 14, i32 0>
|
|
ret <16 x i1> %Shuff
|
|
}
|