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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 18:54:02 +01:00
llvm-mirror/test/CodeGen
Carl Ritson 924e1a4716 [AMDGPU] Add maximum NSA size limit ISA feature
Add maximum NSA size limit as an ISA feature.
Use this to reduce NSA usage on GFX10.1 to avoid stability issues
with 4 and 5 dwords NSA instructions.
Maintain use of longer NSA instructions on GFX10.3.

Note: this also contains some minor fixes for GlobalISel which
did not work correctly with non-NSA form instructions on GFX10.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D103348
2021-07-23 16:16:06 +09:00
..
AArch64 [AArch64] Regenerate test arm64-ccmp.ll 2021-07-22 15:03:05 -07:00
AMDGPU [AMDGPU] Add maximum NSA size limit ISA feature 2021-07-23 16:16:06 +09:00
ARC
ARM ARM: don't return by popping PC if we have to adjust the stack afterwards. 2021-07-21 09:35:14 +01:00
AVR
BPF
Generic
Hexagon
Inputs
Lanai
M68k
Mips
MIR
MSP430
NVPTX
PowerPC [PowerPC] Implement XL compatible behavior of __compare_and_swap 2021-07-23 01:16:02 +00:00
RISCV [SelectionDAG][RISCV] Add tests showing missed scalable-splat optimizations 2021-07-23 06:58:16 +01:00
SPARC
SystemZ
Thumb
Thumb2
VE
WebAssembly [WebAssembly] Implementation of global.get/set for reftypes in LLVM IR 2021-07-22 22:07:24 +02:00
WinCFGuard
WinEH
X86 [X86] Add test case simplified from PR51175. NFC 2021-07-22 23:22:39 -07:00
XCore