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https://github.com/RPCS3/llvm-mirror.git
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f2ee7fe9fe
This adds new instructions to manipluate tagged pointers, and to load and store the tags associated with memory. Patch by Pablo Barrio, David Spickett and Oliver Stannard! Differential revision: https://reviews.llvm.org/D52490 llvm-svn: 343572
396 lines
14 KiB
C++
396 lines
14 KiB
C++
//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the AArch64 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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#include "AArch64FrameLowering.h"
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#include "AArch64ISelLowering.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64RegisterInfo.h"
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#include "AArch64SelectionDAGInfo.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "AArch64GenSubtargetInfo.inc"
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namespace llvm {
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class GlobalValue;
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class StringRef;
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class Triple;
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class AArch64Subtarget final : public AArch64GenSubtargetInfo {
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public:
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enum ARMProcFamilyEnum : uint8_t {
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Others,
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CortexA35,
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CortexA53,
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CortexA55,
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CortexA57,
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CortexA72,
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CortexA73,
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CortexA75,
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Cyclone,
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ExynosM1,
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ExynosM3,
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Falkor,
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Kryo,
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Saphira,
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ThunderX2T99,
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ThunderX,
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ThunderXT81,
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ThunderXT83,
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ThunderXT88
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};
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protected:
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/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
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ARMProcFamilyEnum ARMProcFamily = Others;
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bool HasV8_1aOps = false;
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bool HasV8_2aOps = false;
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bool HasV8_3aOps = false;
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bool HasV8_4aOps = false;
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bool HasV8_5aOps = false;
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bool HasFPARMv8 = false;
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bool HasNEON = false;
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bool HasCrypto = false;
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bool HasDotProd = false;
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bool HasCRC = false;
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bool HasLSE = false;
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bool HasRAS = false;
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bool HasRDM = false;
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bool HasPerfMon = false;
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bool HasFullFP16 = false;
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bool HasFP16FML = false;
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bool HasSPE = false;
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// ARMv8.4 Crypto extensions
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bool HasSM4 = true;
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bool HasSHA3 = true;
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bool HasSHA2 = true;
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bool HasAES = true;
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bool HasLSLFast = false;
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bool HasSVE = false;
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bool HasRCPC = false;
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bool HasAggressiveFMA = false;
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// Armv8.5-A Extensions
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bool HasAlternativeNZCV = false;
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bool HasFRInt3264 = false;
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bool HasSpecRestrict = false;
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bool HasSpecCtrl = false;
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bool HasPredCtrl = false;
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bool HasCCDP = false;
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bool HasBTI = false;
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bool HasRandGen = false;
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bool HasMTE = false;
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// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
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bool HasZeroCycleRegMove = false;
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// HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
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bool HasZeroCycleZeroing = false;
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bool HasZeroCycleZeroingGP = false;
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bool HasZeroCycleZeroingFP = false;
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bool HasZeroCycleZeroingFPWorkaround = false;
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// StrictAlign - Disallow unaligned memory accesses.
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bool StrictAlign = false;
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// NegativeImmediates - transform instructions with negative immediates
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bool NegativeImmediates = true;
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// Enable 64-bit vectorization in SLP.
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unsigned MinVectorRegisterBitWidth = 64;
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bool UseAA = false;
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bool PredictableSelectIsExpensive = false;
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bool BalanceFPOps = false;
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bool CustomAsCheapAsMove = false;
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bool ExynosAsCheapAsMove = false;
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bool UsePostRAScheduler = false;
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bool Misaligned128StoreIsSlow = false;
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bool Paired128IsSlow = false;
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bool STRQroIsSlow = false;
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bool UseAlternateSExtLoadCVTF32Pattern = false;
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bool HasArithmeticBccFusion = false;
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bool HasArithmeticCbzFusion = false;
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bool HasFuseAddress = false;
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bool HasFuseAES = false;
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bool HasFuseCryptoEOR = false;
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bool HasFuseCCSelect = false;
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bool HasFuseLiterals = false;
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bool DisableLatencySchedHeuristic = false;
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bool UseRSqrt = false;
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uint8_t MaxInterleaveFactor = 2;
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uint8_t VectorInsertExtractBaseCost = 3;
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uint16_t CacheLineSize = 0;
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uint16_t PrefetchDistance = 0;
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uint16_t MinPrefetchStride = 1;
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unsigned MaxPrefetchIterationsAhead = UINT_MAX;
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unsigned PrefFunctionAlignment = 0;
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unsigned PrefLoopAlignment = 0;
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unsigned MaxJumpTableSize = 0;
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unsigned WideningBaseCost = 0;
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// ReserveXRegister[i] - X#i is not available as a general purpose register.
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BitVector ReserveXRegister;
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// CustomCallUsedXRegister[i] - X#i call saved.
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BitVector CustomCallSavedXRegs;
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bool IsLittle;
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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AArch64FrameLowering FrameLowering;
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AArch64InstrInfo InstrInfo;
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AArch64SelectionDAGInfo TSInfo;
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AArch64TargetLowering TLInfo;
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/// GlobalISel related APIs.
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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private:
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/// initializeSubtargetDependencies - Initializes using CPUString and the
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/// passed in feature string so that we can use initializer lists for
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/// subtarget initialization.
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AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
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StringRef CPUString);
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/// Initialize properties based on the selected processor family.
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void initializeProperties();
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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AArch64Subtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS, const TargetMachine &TM,
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bool LittleEndian);
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const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const AArch64FrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const AArch64TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const AArch64RegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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}
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const CallLowering *getCallLowering() const override;
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const InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool enableMachineScheduler() const override { return true; }
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bool enablePostRAScheduler() const override {
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return UsePostRAScheduler;
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}
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/// Returns ARM processor family.
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/// Avoid this function! CPU specifics should be kept local to this class
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/// and preferably modeled with SubtargetFeatures or properties in
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/// initializeProperties().
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ARMProcFamilyEnum getProcFamily() const {
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return ARMProcFamily;
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}
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bool hasV8_1aOps() const { return HasV8_1aOps; }
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bool hasV8_2aOps() const { return HasV8_2aOps; }
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bool hasV8_3aOps() const { return HasV8_3aOps; }
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bool hasV8_4aOps() const { return HasV8_4aOps; }
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bool hasV8_5aOps() const { return HasV8_5aOps; }
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bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
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bool hasZeroCycleZeroingGP() const { return HasZeroCycleZeroingGP; }
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bool hasZeroCycleZeroingFP() const { return HasZeroCycleZeroingFP; }
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bool hasZeroCycleZeroingFPWorkaround() const {
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return HasZeroCycleZeroingFPWorkaround;
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}
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bool requiresStrictAlign() const { return StrictAlign; }
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bool isXRaySupported() const override { return true; }
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unsigned getMinVectorRegisterBitWidth() const {
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return MinVectorRegisterBitWidth;
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}
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bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
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unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
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bool isXRegCustomCalleeSaved(size_t i) const {
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return CustomCallSavedXRegs[i];
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}
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bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
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bool hasFPARMv8() const { return HasFPARMv8; }
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bool hasNEON() const { return HasNEON; }
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bool hasCrypto() const { return HasCrypto; }
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bool hasDotProd() const { return HasDotProd; }
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bool hasCRC() const { return HasCRC; }
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bool hasLSE() const { return HasLSE; }
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bool hasRAS() const { return HasRAS; }
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bool hasRDM() const { return HasRDM; }
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bool hasSM4() const { return HasSM4; }
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bool hasSHA3() const { return HasSHA3; }
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bool hasSHA2() const { return HasSHA2; }
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bool hasAES() const { return HasAES; }
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bool balanceFPOps() const { return BalanceFPOps; }
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bool predictableSelectIsExpensive() const {
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return PredictableSelectIsExpensive;
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}
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bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
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bool hasExynosCheapAsMoveHandling() const { return ExynosAsCheapAsMove; }
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bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
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bool isPaired128Slow() const { return Paired128IsSlow; }
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bool isSTRQroSlow() const { return STRQroIsSlow; }
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bool useAlternateSExtLoadCVTF32Pattern() const {
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return UseAlternateSExtLoadCVTF32Pattern;
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}
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bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
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bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
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bool hasFuseAddress() const { return HasFuseAddress; }
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bool hasFuseAES() const { return HasFuseAES; }
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bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
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bool hasFuseCCSelect() const { return HasFuseCCSelect; }
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bool hasFuseLiterals() const { return HasFuseLiterals; }
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/// Return true if the CPU supports any kind of instruction fusion.
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bool hasFusion() const {
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return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
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hasFuseAES() || hasFuseCCSelect() || hasFuseLiterals();
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}
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bool useRSqrt() const { return UseRSqrt; }
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unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
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unsigned getVectorInsertExtractBaseCost() const {
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return VectorInsertExtractBaseCost;
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}
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unsigned getCacheLineSize() const { return CacheLineSize; }
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unsigned getPrefetchDistance() const { return PrefetchDistance; }
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unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
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unsigned getMaxPrefetchIterationsAhead() const {
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return MaxPrefetchIterationsAhead;
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}
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unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
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unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
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unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
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unsigned getWideningBaseCost() const { return WideningBaseCost; }
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/// CPU has TBI (top byte of addresses is ignored during HW address
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/// translation) and OS enables it.
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bool supportsAddressTopByteIgnored() const;
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bool hasPerfMon() const { return HasPerfMon; }
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bool hasFullFP16() const { return HasFullFP16; }
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bool hasFP16FML() const { return HasFP16FML; }
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bool hasSPE() const { return HasSPE; }
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bool hasLSLFast() const { return HasLSLFast; }
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bool hasSVE() const { return HasSVE; }
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bool hasRCPC() const { return HasRCPC; }
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bool hasAggressiveFMA() const { return HasAggressiveFMA; }
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bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
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bool hasFRInt3264() const { return HasFRInt3264; }
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bool hasSpecRestrict() const { return HasSpecRestrict; }
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bool hasSpecCtrl() const { return HasSpecCtrl; }
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bool hasPredCtrl() const { return HasPredCtrl; }
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bool hasCCDP() const { return HasCCDP; }
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bool hasBTI() const { return HasBTI; }
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bool hasRandGen() const { return HasRandGen; }
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bool hasMTE() const { return HasMTE; }
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bool isLittleEndian() const { return IsLittle; }
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bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
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bool isTargetIOS() const { return TargetTriple.isiOS(); }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
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bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
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bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
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bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
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bool useAA() const override { return UseAA; }
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bool useSmallAddressing() const {
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switch (TLInfo.getTargetMachine().getCodeModel()) {
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case CodeModel::Kernel:
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// Kernel is currently allowed only for Fuchsia targets,
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// where it is the same as Small for almost all purposes.
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case CodeModel::Small:
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return true;
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default:
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return false;
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}
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}
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/// ClassifyGlobalReference - Find the target operand flags that describe
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/// how a global value should be referenced for the current subtarget.
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unsigned char ClassifyGlobalReference(const GlobalValue *GV,
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const TargetMachine &TM) const;
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unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
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const TargetMachine &TM) const;
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void overrideSchedPolicy(MachineSchedPolicy &Policy,
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unsigned NumRegionInstrs) const override;
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bool enableEarlyIfConversion() const override;
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std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
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bool isCallingConvWin64(CallingConv::ID CC) const {
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switch (CC) {
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case CallingConv::C:
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return isTargetWindows();
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case CallingConv::Win64:
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return true;
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default:
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return false;
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}
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}
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void mirFileLoaded(MachineFunction &MF) const override;
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};
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} // End llvm namespace
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#endif
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