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076a6683eb
We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
76 lines
2.0 KiB
C++
76 lines
2.0 KiB
C++
//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Contains the definition of a TargetInstrInfo class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
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#include "AMDGPU.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "AMDGPUGenInstrInfo.inc"
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#undef GET_INSTRINFO_HEADER
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namespace llvm {
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class AMDGPUSubtarget;
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class MachineFunction;
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class MachineInstr;
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class MachineInstrBuilder;
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class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
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private:
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const AMDGPUSubtarget &ST;
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virtual void anchor();
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protected:
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AMDGPUAS AMDGPUASI;
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public:
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explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
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bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const override;
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/// Return a target-specific opcode if Opcode is a pseudo instruction.
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/// Return -1 if the target-specific opcode for the pseudo instruction does
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/// not exist. If Opcode is not a pseudo instruction, this is identity.
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int pseudoToMCOpcode(int Opcode) const;
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static bool isUniformMMO(const MachineMemOperand *MMO);
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};
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namespace AMDGPU {
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struct RsrcIntrinsic {
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unsigned Intr;
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uint8_t RsrcArg;
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bool IsImage;
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};
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const RsrcIntrinsic *lookupRsrcIntrinsicByIntr(unsigned Intr);
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struct D16ImageDimIntrinsic {
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unsigned Intr;
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unsigned D16HelperIntr;
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};
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const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsicByIntr(unsigned Intr);
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} // end AMDGPU namespace
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} // End llvm namespace
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#endif
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