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fad4cbdb84
Summary: These new image intrinsics contain the texture type as part of their name and have each component of the address/coordinate as individual parameters. This is a preparatory step for implementing the A16 feature, where coordinates are passed as half-floats or -ints, but the Z compare value and texel offsets are still full dwords, making it difficult or impossible to distinguish between A16 on or off in the old-style intrinsics. Additionally, these intrinsics pass the 'texfailpolicy' and 'cachectrl' as i32 bit fields to reduce operand clutter and allow for future extensibility. v2: - gather4 supports 2darray images - fix a bug with 1D images on SI Change-Id: I099f309e0a394082a5901ea196c3967afb867f04 Reviewers: arsenm, rampitec, b-sumner Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D44939 llvm-svn: 329166
100 lines
4.0 KiB
TableGen
100 lines
4.0 KiB
TableGen
//===-- AMDGPUSearchableTables.td - ------------------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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include "llvm/TableGen/SearchableTable.td"
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//===----------------------------------------------------------------------===//
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// Resource intrinsics table.
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//===----------------------------------------------------------------------===//
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class RsrcIntrinsic<AMDGPURsrcIntrinsic intr> : SearchableTable {
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let SearchableFields = ["Intr"];
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let EnumNameField = ?;
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Intrinsic Intr = !cast<Intrinsic>(intr);
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bits<8> RsrcArg = intr.RsrcArg;
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bit IsImage = intr.IsImage;
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}
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foreach intr = !listconcat(AMDGPUBufferIntrinsics,
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AMDGPUImageIntrinsics,
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AMDGPUImageDimIntrinsics,
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AMDGPUImageDimGatherIntrinsics,
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AMDGPUImageDimGetResInfoIntrinsics,
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AMDGPUImageDimAtomicIntrinsics) in {
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def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
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}
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class SourceOfDivergence<Intrinsic intr> : SearchableTable {
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let SearchableFields = ["Intr"];
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let EnumNameField = ?;
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Intrinsic Intr = intr;
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}
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def : SourceOfDivergence<int_amdgcn_workitem_id_x>;
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def : SourceOfDivergence<int_amdgcn_workitem_id_y>;
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def : SourceOfDivergence<int_amdgcn_workitem_id_z>;
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def : SourceOfDivergence<int_amdgcn_interp_mov>;
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def : SourceOfDivergence<int_amdgcn_interp_p1>;
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def : SourceOfDivergence<int_amdgcn_interp_p2>;
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def : SourceOfDivergence<int_amdgcn_mbcnt_hi>;
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def : SourceOfDivergence<int_amdgcn_mbcnt_lo>;
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def : SourceOfDivergence<int_r600_read_tidig_x>;
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def : SourceOfDivergence<int_r600_read_tidig_y>;
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def : SourceOfDivergence<int_r600_read_tidig_z>;
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def : SourceOfDivergence<int_amdgcn_atomic_inc>;
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def : SourceOfDivergence<int_amdgcn_atomic_dec>;
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def : SourceOfDivergence<int_amdgcn_ds_fadd>;
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def : SourceOfDivergence<int_amdgcn_ds_fmin>;
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def : SourceOfDivergence<int_amdgcn_ds_fmax>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_swap>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_add>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_sub>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_smin>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_umin>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_smax>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_umax>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_and>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_or>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_xor>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_inc>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_dec>;
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def : SourceOfDivergence<int_amdgcn_image_atomic_cmpswap>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_swap>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_add>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_sub>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_smin>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_umin>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_smax>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_umax>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_and>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_or>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_xor>;
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def : SourceOfDivergence<int_amdgcn_buffer_atomic_cmpswap>;
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def : SourceOfDivergence<int_amdgcn_ps_live>;
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def : SourceOfDivergence<int_amdgcn_ds_swizzle>;
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foreach intr = AMDGPUImageDimAtomicIntrinsics in
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def : SourceOfDivergence<intr>;
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class D16ImageDimIntrinsic<AMDGPUImageDimIntrinsic intr> : SearchableTable {
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let SearchableFields = ["Intr"];
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let EnumNameField = ?;
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Intrinsic Intr = intr;
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code D16HelperIntr =
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!cast<code>("AMDGPUIntrinsic::SI_image_d16helper_" # intr.P.OpMod # intr.P.Dim.Name);
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}
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foreach intr = !listconcat(AMDGPUImageDimIntrinsics,
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AMDGPUImageDimGatherIntrinsics) in {
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def : D16ImageDimIntrinsic<intr>;
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}
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