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3f7c3f8303
This is a step toward having statically allocated instruciton mapping. We are going to tablegen them eventually, so let us reflect that in the API. NFC. llvm-svn: 302316
44 lines
1.3 KiB
C++
44 lines
1.3 KiB
C++
//===- ARMRegisterBankInfo ---------------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the RegisterBankInfo class for ARM.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
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#define LLVM_LIB_TARGET_ARM_ARMREGISTERBANKINFO_H
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#define GET_REGBANK_DECLARATIONS
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#include "ARMGenRegisterBank.inc"
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namespace llvm {
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class TargetRegisterInfo;
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class ARMGenRegisterBankInfo : public RegisterBankInfo {
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#define GET_TARGET_REGBANK_CLASS
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#include "ARMGenRegisterBank.inc"
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};
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/// This class provides the information for the target register banks.
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class ARMRegisterBankInfo final : public ARMGenRegisterBankInfo {
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public:
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ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
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const RegisterBank &
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getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
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const InstructionMapping &
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getInstrMapping(const MachineInstr &MI) const override;
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};
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} // End llvm namespace.
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#endif
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