Simi Pallipurath a92dd7a309 [ARM]Decoding MSR with unpredictable destination register causes an assert ... This patch handling: Enable parsing of raw encodings of system registers . Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing. Disassemble msr/mrs with unpredictable sysregs as SoftFail. Fix regression due to SoftFailing some encodings. Patch by Chris Ryder Differential revision:https://reviews.llvm.org/D43374 llvm-svn: 326803		2018-03-06 15:21:19 +00:00
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ARMDisassembler.cpp	[ARM]Decoding MSR with unpredictable destination register causes an assert	2018-03-06 15:21:19 +00:00
CMakeLists.txt
LLVMBuild.txt	[ARM] Re-commit r324600 with fixed LLVMBuild.txt	2018-02-08 14:31:22 +00:00