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45b647d5eb
This header includes CodeGen headers, and is not, itself, included by any Target headers, so move it into CodeGen to match the layering of its implementation. llvm-svn: 317647
99 lines
3.5 KiB
C++
99 lines
3.5 KiB
C++
//===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MSP430 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
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#define LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
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#include "MSP430RegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "MSP430GenInstrInfo.inc"
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namespace llvm {
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class MSP430Subtarget;
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/// MSP430II - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace MSP430II {
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enum {
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SizeShift = 2,
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SizeMask = 7 << SizeShift,
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SizeUnknown = 0 << SizeShift,
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SizeSpecial = 1 << SizeShift,
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Size2Bytes = 2 << SizeShift,
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Size4Bytes = 3 << SizeShift,
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Size6Bytes = 4 << SizeShift
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};
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}
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class MSP430InstrInfo : public MSP430GenInstrInfo {
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const MSP430RegisterInfo RI;
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virtual void anchor();
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public:
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explicit MSP430InstrInfo(MSP430Subtarget &STI);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const TargetRegisterInfo &getRegisterInfo() const { return RI; }
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill,
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int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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// Branch folding goodness
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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int64_t getFramePoppedByCallee(const MachineInstr &I) const {
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assert(isFrameInstr(I) && "Not a frame instruction");
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assert(I.getOperand(1).getImm() >= 0 && "Size must not be negative");
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return I.getOperand(1).getImm();
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}
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};
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}
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#endif
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